PIC18F6393 Datasheet, PDF (46/58 Pages) Microchip Technology – 64/80-Pin High Performance,

PIC18F6393/6493/8393/8493
FIGURE 4-3:
A/D CONVERSION TIMING
BSF ADCON0, GO
Q4
A/D CLK⁽¹⁾
132
A/D DATA
(Note 2)
131
130
11 10 9 ^{. . . . . .} 3
2
1
0
ADRES
ADIF
OLD_DATA
NEW_DATA
TCY
GO
SAMPLE
SAMPLING STOPPED
DONE
Note 1:
2:
If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction
to be executed.
This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
TABLE 4-2: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol
Characteristic
Min Max Units
Conditions
130 TAD
A/D Clock Period
PIC18FXXXX
PIC18LFXXXX
0.8 12.5⁽¹⁾ μs TOSC based, VREF ≥ 3.0V
1.4 25.0⁽¹⁾ μs VDD = 3.0V; TOSC based,
VREF full range
PIC18FXXXX
—
1
μs A/D RC mode
PIC18LFXXXX
—
3
μs VDD = 3.0V; A/D RC mode
131 TCNV Conversion Time
(not including acquisition time)⁽²⁾
132 TACQ Acquisition Time⁽³⁾
13
14
TAD
1.4
—
μs
135 TSWC Switching Time from Convert → Sample
— (Note 4)
137 TDIS Discharge Time
0.2
—
μs
Note 1:
2:
3:
The time of the A/D clock period is dependent on the device frequency and the TAD clock divider.
ADRES registers may be read on the following TCY cycle.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (VDD to VSS or VSS to VDD). The source impedance (RS) on the input channels is 50Ω.
4: On the following cycle of the device clock.
DS39896A-page 44
Preliminary
© 2007 Microchip Technology Inc.