PIC18F6393 Datasheet, PDF (28/58 Pages) Microchip Technology – 64/80-Pin High Performance,

PIC18F6393/6493/8393/8493
TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number _{Pin Buffer}
TQFP ^{Type Type}
Description
PORTG is a bidirectional I/O port.
RG0/SEG30
RG0
SEG30
5
I/O ST
Digital I/O.
O Analog SEG30 output for LCD.
RG1/TX2/CK2/SEG29
RG1
TX2
CK2
SEG29
6
I/O ST
Digital I/O.
O—
AUSART2 asynchronous transmit.
I/O ST
AUSART2 synchronous clock (see related RX2/DT2).
O Analog SEG29 output for LCD.
RG2/RX2/DT2/SEG28
RG2
RX2
DT2
SEG28
7
I/O ST
Digital I/O.
I
ST
AUSART2 asynchronous receive.
I/O ST
AUSART2 synchronous data (see related TX2/CK2).
O Analog SEG28 output for LCD.
RG3/SEG27
RG3
SEG27
8
I/O ST
Digital I/O.
O Analog SEG27 output for LCD.
RG4/SEG26
RG4
SEG26
10
I/O ST
Digital I/O.
O Analog SEG26 output for LCD.
RG5
See MCLR/VPP/RG5 pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
DS39896A-page 26
Preliminary
© 2007 Microchip Technology Inc.