PIC18F6393 Datasheet, PDF (13/58 Pages) Microchip Technology – 64/80-Pin High Performance,

PIC18F6393/6493/8393/8493
TABLE 1-2: PIC18F6X93 PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number _{Pin Buffer}
TQFP ^{Type Type}
Description
MCLR/VPP/RG5
MCLR
VPP
RG5
7
Master Clear (input) or programming voltage (input).
I
ST
Master Clear (Reset) input. This pin is an active-low
Reset to the device.
P
Programming voltage input.
I
ST
Digital input.
OSC1/CLKI/RA7
OSC1
CLKI
RA7
39
Oscillator crystal or external clock input.
I
ST
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode; CMOS otherwise.
I CMOS External clock source input. Always associated
with pin function OSC1. (See related OSC1/CLKI,
OSC2/CLKO pins.)
I/O TTL
General purpose I/O pin.
OSC2/CLKO/RA6
OSC2
CLKO
RA6
40
Oscillator crystal or clock output.
O—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
O—
In RC mode, OSC2 pin outputs CLKO, which has
1/4 the frequency of OSC1 and denotes the
instruction cycle rate.
I/O TTL
General purpose I/O pin.
Legend: TTL = TTL compatible input
ST = Schmitt Trigger input with CMOS levels
I = Input
P = Power
CMOS
Analog
O
OD
= CMOS compatible input or output
= Analog input
= Output
= Open-Drain (no P diode to VDD)
Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set.
2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared.
© 2007 Microchip Technology Inc.
Preliminary
DS39896A-page 11