PIC18F2525 Datasheet, PDF (385/390 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
Timer3 .............................................................................. 135
16-Bit Read/Write Mode ........................................... 137
Associated Registers ............................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt ............................................ 135, 137
Special Event Trigger (CCP) .................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
Timing Diagrams
A/D Conversion ........................................................ 360
Acknowledge Sequence .......................................... 194
Asynchronous Reception ......................................... 214
Asynchronous Transmission .................................... 212
Asynchronous Transmission
(Back to Back) ................................................. 212
Automatic Baud Rate Calculation ............................ 210
Auto-Wake-up Bit (WUE) During
Normal Operation ............................................ 215
Auto-Wake-up Bit (WUE) During Sleep ................... 215
Baud Rate Generator with Clock Arbitration ............ 188
BRG Overflow Sequence ......................................... 210
BRG Reset Due to SDA Arbitration
During Start Condition ..................................... 197
Brown-out Reset (BOR) ........................................... 346
Bus Collision During a Repeated Start
Condition (Case 1) ........................................... 198
Bus Collision During a Repeated Start
Condition (Case 2) ........................................... 198
Bus Collision During a
Start Condition (SCL = 0) ................................. 197
Bus Collision During a
Stop Condition (Case 1) .................................. 199
Bus Collision During a
Stop Condition (Case 2) .................................. 199
Bus Collision During Start
Condition (SDA Only) ...................................... 196
Bus Collision for Transmit and
Acknowledge ................................................... 195
Capture/Compare/PWM (CCP) ................................ 348
CLKO and I/O .......................................................... 345
Clock Synchronization ............................................. 181
Clock/Instruction Cycle .............................................. 57
Example SPI Master Mode (CKE = 0) ..................... 350
Example SPI Master Mode (CKE = 1) ..................... 351
Example SPI Slave Mode (CKE = 0) ....................... 352
Example SPI Slave Mode (CKE = 1) ....................... 353
External Clock (All Modes except PLL) .................... 343
Fail-Safe Clock Monitor ............................................ 262
First Start Bit Timing ................................................ 189
Full-Bridge PWM Output .......................................... 153
Half-Bridge PWM Output ......................................... 152
High/Low-Voltage Detect Characteristics ................ 340
High-Voltage Detect Operation
(VDIRMAG = 1) ................................................ 246
I²C Bus Data ............................................................ 354
I²C Bus Start/Stop Bits ............................................. 354
I²C Master Mode (7 or
10-Bit Transmission) ........................................ 192
I²C Master Mode (7-Bit Reception) .......................... 193
I²C Slave Mode (10-Bit Reception, SEN = 0) .......... 178
I²C Slave Mode (10-Bit Reception, SEN = 1) .......... 183
I²C Slave Mode (10-Bit Transmission) ..................... 179
I²C Slave Mode (7-Bit Reception, SEN = 0) ............ 176
I²C Slave Mode (7-Bit Reception, SEN = 1) ............ 182
I²C Slave Mode (7-Bit Transmission) ...................... 177
I²C Slave Mode General Call Address
Sequence (7 or 10-Bit Address Mode) ............ 184
I²C Stop Condition Receive or
Transmit Mode ................................................. 194
Low-Voltage Detect Operation
(VDIRMAG = 0) ............................................... 245
Master SSP I²C Bus Data ....................................... 356
Master SSP I²C Bus Start/Stop Bits ........................ 356
Parallel Slave Port
(PIC18F4410/4510/4515/4610) ....................... 349
Parallel Slave Port (PSP) Read ............................... 121
Parallel Slave Port (PSP) Write ............................... 121
PWM Auto-Shutdown (PRSEN = 0,
Auto-Restart Disabled) .................................... 158
PWM Auto-Shutdown (PRSEN = 1,
Auto-Restart Enabled) ..................................... 158
PWM Direction Change ........................................... 155
PWM Direction Change at Near
100% Duty Cycle ............................................. 155
PWM Output ............................................................ 144
Repeat Start Condition ............................................ 190
Reset, Watchdog Timer (WDT),
Oscillator Start-up Timer (OST),
Power-up Timer (PWRT) ................................. 346
Send Break Character Sequence ............................ 216
Slave Synchronization ............................................. 167
Slow Rise Time (MCLR Tied to VDD,
VDD Rise > TPWRT) ............................................ 47
SPI Mode (Master Mode) ........................................ 166
SPI Mode (Slave Mode, CKE = 0) ........................... 168
SPI Mode (Slave Mode, CKE = 1) ........................... 168
Synchronous Reception (Master Mode,
SREN) ............................................................. 219
Synchronous Transmission ..................................... 217
Synchronous Transmission
(Through TXEN) .............................................. 218
Time-out Sequence on POR w/PLL
Enabled (MCLR Tied to VDD) ............................ 47
Time-out Sequence on Power-up
(MCLR Not Tied to VDD, Case 1) ...................... 46
Time-out Sequence on Power-up
(MCLR Not Tied to VDD, Case 2) ...................... 46
Time-out Sequence on Power-up
(MCLR Tied to VDD, VDD Rise < TPWRT) ........... 46
Timer0 and Timer1 External Clock .......................... 347
Transition for Entry to Idle Mode ............................... 38
Transition for Entry to SEC_RUN Mode .................... 35
Transition for Entry to Sleep Mode ............................ 37
Transition for Two-Speed Start-up
(INTOSC to HSPLL) ........................................ 260
Transition for Wake from Idle to
Run Mode .......................................................... 38
Transition for Wake from Sleep (HSPLL) .................. 37
Transition from RC_RUN Mode to
PRI_RUN Mode ................................................. 36
Transition from SEC_RUN Mode to
PRI_RUN Mode (HSPLL) .................................. 35
Transition to RC_RUN Mode ..................................... 36
USART Synchronous Receive
(Master/Slave) ................................................. 358
USART Synchronous Transmission
(Master/Slave) ................................................. 358
 2004 Microchip Technology Inc.
Preliminary
DS39626B-page 383