PIC18F2525 Datasheet, PDF (380/390 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
Flash Program Memory ...................................................... 73
Associated Registers ................................................. 81
Control Registers ....................................................... 74
EECON1 and EECON2 ..................................... 74
TABLAT (Table Latch) Register ......................... 76
TBLPTR (Table Pointer) Register ...................... 76
Erase Sequence ........................................................ 78
Erasing ....................................................................... 78
Operation During Code-Protect ................................. 81
Reading ...................................................................... 77
Table Pointer
Boundaries Based on Operation ........................ 76
Operations with TBLRD
and TBLWT (table) .................................... 76
Table Pointer Boundaries .......................................... 76
Table Reads and Table Writes .................................. 73
Write Sequence ......................................................... 79
Writing ........................................................................ 79
Protection Against Spurious Writes ................... 81
Unexpected Termination .................................... 81
Write Verify ........................................................ 81
FSCM. See Fail-Safe Clock Monitor.
G
GOTO ............................................................................... 288
H
Hardware Multiplier ............................................................ 89
Introduction ................................................................ 89
Operation ................................................................... 89
Performance Comparison .......................................... 89
High/Low-Voltage Detect ................................................. 243
Applications .............................................................. 246
Associated Registers ............................................... 247
Characteristics ......................................................... 340
Current Consumption ............................................... 245
Effects of a Reset ..................................................... 247
Operation ................................................................. 244
During Sleep .................................................... 247
Setup ........................................................................ 245
Start-up Time ........................................................... 245
Typical Application ................................................... 246
HLVD. See High/Low-Voltage Detect. ............................. 243
I
I/O Ports ........................................................................... 105
I²C Mode (MSSP)
Acknowledge Sequence Timing ............................... 194
Baud Rate Generator ............................................... 187
Bus Collision
During a Repeated Start
Condition .................................................. 198
During a Start Condition ................................... 196
During a Stop Condition ................................... 199
Clock Arbitration ....................................................... 188
Clock Stretching ....................................................... 180
10-Bit Slave Receive Mode (SEN = 1) ............. 180
10-Bit Slave Transmit Mode ............................. 180
7-Bit Slave Receive Mode (SEN = 1) ............... 180
7-Bit Slave Transmit Mode ............................... 180
Clock Synchronization and the
CKP bit (SEN = 1) ............................................ 181
Effects of a Reset ..................................................... 195
General Call Address Support ................................. 184
I²C Clock Rate w/BRG ............................................. 187
Master Mode ............................................................ 185
Operation ......................................................... 186
Reception ........................................................ 191
Repeated Start Condition Timing .................... 190
Start Condition Timing ..................................... 189
Transmission ................................................... 191
Multi-Master Communication, Bus Collision
and Arbitration ................................................. 195
Multi-Master Mode ................................................... 195
Operation ................................................................. 174
Read/Write Bit Information (R/W Bit) ............... 174, 175
Registers ................................................................. 170
Serial Clock (RC3/SCK/SCL) ................................... 175
Slave Mode .............................................................. 174
Addressing ....................................................... 174
Reception ........................................................ 175
Transmission ................................................... 175
Sleep Operation ....................................................... 195
Stop Condition Timing ............................................. 194
ID Locations ............................................................. 249, 266
INCF ................................................................................ 288
INCFSZ ............................................................................ 289
In-Circuit Debugger .......................................................... 266
In-Circuit Serial Programming (ICSP) ...................... 249, 266
Indexed Literal Offset Addressing
and Standard PIC18 Instructions ............................. 314
Indexed Literal Offset Mode ............................................. 314
Indirect Addressing ............................................................ 68
INFSNZ ............................................................................ 289
Initialization Conditions for all Registers ...................... 49–52
Instruction Cycle ................................................................ 57
Clocking Scheme ....................................................... 57
Instruction Flow/Pipelining ................................................. 57
Instruction Set .................................................................. 267
ADDLW .................................................................... 273
ADDWF .................................................................... 273
ADDWF (Indexed Literal Offset Mode) .................... 315
ADDWFC ................................................................. 274
ANDLW .................................................................... 274
ANDWF .................................................................... 275
BC ............................................................................ 275
BCF ......................................................................... 276
BN ............................................................................ 276
BNC ......................................................................... 277
BNN ......................................................................... 277
BNOV ...................................................................... 278
BNZ ......................................................................... 278
BOV ......................................................................... 281
BRA ......................................................................... 279
BSF .......................................................................... 279
BSF (Indexed Literal Offset Mode) .......................... 315
BTFSC ..................................................................... 280
BTFSS ..................................................................... 280
BTG ......................................................................... 281
BZ ............................................................................ 282
CALL ........................................................................ 282
CLRF ....................................................................... 283
CLRWDT ................................................................. 283
COMF ...................................................................... 284
CPFSEQ .................................................................. 284
CPFSGT .................................................................. 285
CPFSLT ................................................................... 285
DAW ........................................................................ 286
DCFSNZ .................................................................. 287
DECF ....................................................................... 286
DS39626B-page 378
Preliminary
 2004 Microchip Technology Inc.