PIC18F2525 Datasheet, PDF (384/390 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
SSPCON1 (MSSP Control 1, I²C Mode) ................. 172
SSPCON1 (MSSP Control 1, SPI Mode) ................. 163
SSPCON2 (MSSP Control 2, I²C Mode) ................. 173
SSPSTAT (MSSP Status, I²C Mode) ....................... 171
SSPSTAT (MSSP Status, SPI Mode) ...................... 162
Status ......................................................................... 66
STKPTR (Stack Pointer) ............................................ 55
T0CON (Timer0 Control) .......................................... 123
T1CON (Timer1 Control) .......................................... 127
T2CON (Timer2 Control) .......................................... 133
T3CON (Timer3 Control) .......................................... 135
TRISE (PORTE/PSP Control) .................................. 118
TXSTA (Transmit Status and Control) ..................... 202
WDTCON (Watchdog Timer Control) ....................... 259
RESET ............................................................................. 297
Reset State of Registers .................................................... 48
Resets ........................................................................ 41, 249
Brown-out Reset (BOR) ........................................... 249
Oscillator Start-up Timer (OST) ............................... 249
Power-on Reset (POR) ............................................ 249
Power-up Timer (PWRT) ......................................... 249
RETFIE ............................................................................ 298
RETLW ............................................................................. 298
RETURN .......................................................................... 299
Return Address Stack ........................................................ 54
Associated Registers ................................................. 54
Return Stack Pointer (STKPTR) ........................................ 55
Revision History ............................................................... 371
RLCF ................................................................................ 299
RLNCF ............................................................................. 300
RRCF ............................................................................... 300
RRNCF ............................................................................. 301
S
SCK .................................................................................. 161
SDI ................................................................................... 161
SDO ................................................................................. 161
SEC_IDLE Mode ................................................................ 38
SEC_RUN Mode ................................................................ 34
Serial Clock, SCK ............................................................. 161
Serial Data In (SDI) .......................................................... 161
Serial Data Out (SDO) ..................................................... 161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 301
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
SLEEP .............................................................................. 302
Sleep
OSC1 and OSC2 Pin States ...................................... 31
Software Simulator (MPLAB SIM) .................................... 318
Software Simulator (MPLAB SIM30) ................................ 318
Special Event Trigger. See Compare (ECCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ............................................ 249
Special Function Registers ................................................ 62
Map ............................................................................ 62
SPI Mode (MSSP)
Associated Registers ............................................... 169
Bus Mode Compatibility ........................................... 169
Effects of a Reset ..................................................... 169
Enabling SPI I/O ...................................................... 165
Master Mode ............................................................ 166
Master/Slave Connection ......................................... 165
Operation ................................................................. 164
Operation in Power Managed Modes ...................... 169
Serial Clock .............................................................. 161
Serial Data In ........................................................... 161
Serial Data Out ........................................................ 161
Slave Mode .............................................................. 167
Slave Select ............................................................. 161
Slave Select Synchronization .................................. 167
SPI Clock ................................................................. 166
Typical Connection .................................................. 165
SS .................................................................................... 161
SSPOV ............................................................................ 191
SSPOV Status Flag ......................................................... 191
SSPSTAT Register
R/W Bit ............................................................ 174, 175
Stack Full/Underflow Resets .............................................. 56
Standard Instructions ....................................................... 267
SUBFSR .......................................................................... 313
SUBFWB ......................................................................... 302
SUBLW ............................................................................ 303
SUBULNK ........................................................................ 313
SUBWF ............................................................................ 303
SUBWFB ......................................................................... 304
SWAPF ............................................................................ 304
T
Table Reads/Table Writes ................................................. 56
TBLRD ............................................................................. 305
TBLWT ............................................................................. 306
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 123
Associated Registers ............................................... 125
Operation ................................................................. 124
Overflow Interrupt .................................................... 125
Prescaler ................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ............................... 124
Source Select (T0CS Bit) ......................................... 124
Switching Prescaler Assignment ............................. 125
Timer1 .............................................................................. 127
16-Bit Read/Write Mode .......................................... 129
Associated Registers ............................................... 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Layout Considerations ..................................... 130
Low-Power Option ........................................... 129
Overflow Interrupt .................................................... 127
Resetting, Using the CCP
Special Event Trigger ...................................... 130
Special Event Trigger (ECCP) ................................. 148
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Real-Time Clock ....................................... 130
Timer2 .............................................................................. 133
Associated Registers ............................................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2 to PR2 Match Interrupt .......................... 144, 149
DS39626B-page 382
Preliminary
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