PIC18F2525 Datasheet, PDF (189/390 Pages) Microchip Technology – 28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology

PIC18F2525/2620/4525/4620
17.4.7 BAUD RATE
In I²C Master mode, the Baud Rate Generator (BRG)
reload value is placed in the lower 7 bits of the
SSPADD register (Figure 17-17). When a write occurs
to SSPBUF, the Baud Rate Generator will automatically
begin counting. The BRG counts down to ‘0’ and stops
until another reload has taken place. The BRG count is
decremented twice per instruction cycle (TCY) on the
Q2 and Q4 clocks. In I²C Master mode, the BRG is
reloaded automatically.
Once the given operation is complete (i.e., transmis-
sion of the last data bit is followed by ACK), the internal
clock will automatically stop counting and the SCL pin
will remain in its last state.
Table 17-3 demonstrates clock rates based on
instruction cycles and the BRG value loaded into
SSPADD.
FIGURE 17-17:
BAUD RATE GENERATOR BLOCK DIAGRAM
SSPM3:SSPM0
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
CLKO
BRG Down Counter
FOSC/4
TABLE 17-3: I²C™ CLOCK RATE W/BRG
Fosc
40 MHz
40 MHz
40 MHz
16 MHz
16 MHz
16 MHz
4 MHz
4 MHz
4 MHz
Note 1:
FCY
FCY*2
BRG Value
FSCL
(2 Rollovers of BRG)
10 MHz
20 MHz
18h
400 kHz⁽¹⁾
10 MHz
20 MHz
1Fh
312.5 kHz
10 MHz
4 MHz
20 MHz
8 MHz
63h
100 kHz
09h
400 kHz⁽¹⁾
4 MHz
8 MHz
0Ch
308 kHz
4 MHz
1 MHz
8 MHz
2 MHz
27h
100 kHz
02h
333 kHz⁽¹⁾
1 MHz
2 MHz
09h
100 kHz
1 MHz
2 MHz
00h
1 MHz⁽¹⁾
Note 1: The I²C interface does not conform to the 400 kHz I²C specification (which applies
to rates greater than 100 kHz) in all details, but may be used with care where
higher rates are required by the application.
 2004 Microchip Technology Inc.
Preliminary
DS39626B-page 187