PIC16F882-I Datasheet, PDF (36/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers

PIC16F882/883/884/886/887
2.2.2.6 PIR1 Register
The PIR1 register contains the interrupt flag bits, as
shown in Register 2-6.
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the Global
Enable bit, GIE of the INTCON register.
User software should ensure the
appropriate interrupt flag bits are clear prior
to enabling an interrupt.
REGISTER 2-6: PIR1: PERIPHERAL INTERRUPT REQUEST REGISTER 1
U-0
—
bit 7
R/W-0
ADIF
R-0
RCIF
R-0
TXIF
R/W-0
SSPIF
R/W-0
CCP1IF
R/W-0
TMR2IF
R/W-0
TMR1IF
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = A/D conversion complete (must be cleared in software)
0 = A/D conversion has not completed or has not been started
bit 5
RCIF: EUSART Receive Interrupt Flag bit
1 = The EUSART receive buffer is full (cleared by reading RCREG)
0 = The EUSART receive buffer is not full
bit 4
TXIF: EUSART Transmit Interrupt Flag bit
1 = The EUSART transmit buffer is empty (cleared by writing to TXREG)
0 = The EUSART transmit buffer is full
bit 3
SSPIF: Master Synchronous Serial Port (MSSP) Interrupt Flag bit
1 = The MSSP interrupt condition has occurred, and must be cleared in software before returning from the
Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/reception has taken place
I²C Slave/Master
A transmission/reception has taken place
I²C Master
The initiated Start condition was completed by the MSSP module
The initiated Stop condition was completed by the MSSP module
The initiated restart condition was completed by the MSSP module
The initiated Acknowledge condition was completed by the MSSP module
A Start condition occurred while the MSSP module was idle (Multi-master system)
A Stop condition occurred while the MSSP module was idle (Multi-master system)
0 = No MSSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: Timer2 to PR2 Interrupt Flag bit
1 = A Timer2 to PR2 match occurred (must be cleared in software)
0 = No Timer2 to PR2 match occurred
bit 0
TMR1IF: Timer1 Overflow Interrupt Flag bit
1 = The TMR1 register overflowed (must be cleared in software)
0 = The TMR1 register did not overflow
DS41291F-page 34
© 2009 Microchip Technology Inc.