PIC16F882-I Datasheet, PDF (195/328 Pages) Microchip Technology – 28/40/44-Pin, Enhanced Flash-Based 8-Bit CMOS Microcontrollers

PIC16F882/883/884/886/887
13.4.3 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the Start and Stop
conditions. The Stop (P) and Start (S) bits are cleared
from a Reset, or when the MSSP module is disabled.
Control of the I²C bus may be taken when the P bit is
set, or the bus is idle, with both the S and P bits clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• Start condition
• Stop condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start condition
13.4.4 I²C™ MASTER MODE SUPPORT
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1. Assert a Start condition on SDA and SCL.
2. Assert a Repeated Start condition on SDA and
SCL.
3. Write to the SSPBUF register initiating
transmission of data/address.
4. Generate a Stop condition on SDA and SCL.
5. Configure the I²C port to receive data.
6. Generate an Acknowledge condition at the end
of a received byte of data.
Note:
The MSSP module, when configured in I²C
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a Start condition and
immediately write the SSPBUF register to
imitate transmission, before the Start
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
FIGURE 13-10: MSSP BLOCK DIAGRAM (I²C™ MASTER MODE)
Read
Internal
Data Bus
Write
SSPBUF
SDA
SDA In
SSPSR
MSb
Shift
Clock
LSb
SCL
Start bit, Stop bit,
Acknowledge
Generate
SSPM<3:0>
SSPADD<6:0>
Baud
Rate
Generator
SCL In
Bus Collision
Start bit Detect
Stop bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
End of XMIT/RCV
Note: I/O pins have diode protection to VDD and VSS.
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
© 2009 Microchip Technology Inc.
DS41291F-page 193