PIC16F887I-PT Datasheet, PDF (327/338 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers

PIC16F882/883/884/886/887
EUSART ........................................................................... 155
Associated Registers
Baud Rate Generator........................................ 167
Asynchronous Mode ................................................. 157
12-bit Break Transmit and Receive .................. 173
Associated Registers
Receive..................................................... 163
Transmit.................................................... 159
Auto-Wake-up on Break ................................... 172
Baud Rate Generator (BRG) ............................ 167
Clock Accuracy ................................................. 164
Receiver............................................................ 160
Setting up 9-bit Mode with Address Detect....... 162
Transmitter........................................................ 157
Baud Rate Generator (BRG)
Auto Baud Rate Detect ..................................... 171
Baud Rate Error, Calculating ............................ 167
Baud Rates, Asynchronous Modes .................. 168
Formulas ........................................................... 167
High Baud Rate Select (BRGH Bit) .................. 167
Synchronous Master Mode ............................... 175, 179
Associated Registers
Receive..................................................... 178
Transmit.................................................... 176
Reception.......................................................... 177
Requirements, Synchronous Receive .............. 270
Requirements, Synchronous Transmission ...... 270
Timing Diagram, Synchronous Receive ........... 270
Timing Diagram, Synchronous Transmission ... 270
Transmission .................................................... 175
Synchronous Slave Mode
Associated Registers
Receive..................................................... 180
Transmit.................................................... 179
Reception.......................................................... 180
Transmission .................................................... 179
F
Fail-Safe Clock Monitor....................................................... 75
Fail-Safe Condition Clearing ....................................... 75
Fail-Safe Detection ..................................................... 75
Fail-Safe Operation..................................................... 75
Reset or Wake-up from Sleep..................................... 75
Firmware Instructions........................................................ 235
Flash Program Memory .................................................... 115
Writing....................................................................... 121
Fuses. See Configuration Bits
G
General Call Address Support .......................................... 196
General Purpose Register File............................................ 24
I
I²C (MSSP Module)
ACK Pulse......................................................... 193, 194
Addressing ................................................................ 194
Read/Write Bit Information (R/W Bit) ........................ 194
Reception.................................................................. 194
Serial Clock (RC3/SCK/SCL).................................... 194
Slave Mode ............................................................... 193
Transmission............................................................. 194
I²C Master Mode Reception.............................................. 202
I²C Master Mode Repeated Start Condition Timing.......... 201
I²C Module
Acknowledge Sequence Timing................................ 205
Baud Rate Generator................................................ 199
BRG Block Diagram ................................................. 199
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 209
BRG Timing .............................................................. 199
Bus Collision
Acknowledge .................................................... 207
Repeated Start Condition ................................. 210
Repeated Start Condition Timing (Case1)........ 210
Repeated Start Condition Timing (Case2)........ 210
Start Condition.................................................. 208
Start Condition Timing .............................. 208, 209
Stop Condition .................................................. 211
Stop Condition Timing (Case 1) ....................... 211
Stop Condition Timing (Case 2) ....................... 211
Bus Collision timing .................................................. 207
Clock Arbitration ....................................................... 206
Clock Arbitration Timing (Master Transmit) .............. 206
Effect of a Reset ....................................................... 206
General Call Address Support .................................. 196
Master Mode............................................................. 197
Master Mode 7-bit Reception Timing........................ 204
Master Mode Operation............................................ 198
Master Mode Start Condition Timing ........................ 200
Master Mode Support ............................................... 197
Master Mode Transmission ...................................... 202
Master Mode Transmit Sequence ............................ 198
Multi-Master Mode.................................................... 207
Repeat Start Condition Timing Waveform ................ 201
Sleep Operation........................................................ 206
Stop Condition Receive or Transmit Timing ............. 206
Stop Condition Timing .............................................. 205
Waveforms for 7-bit Reception ................................. 195
Waveforms for 7-bit Transmission............................ 195
ID Locations...................................................................... 231
In-Circuit Debugger........................................................... 233
In-Circuit Serial Programming (ICSP)............................... 231
Indirect Addressing, INDF and FSR registers..................... 39
Instruction Format............................................................. 235
Instruction Set................................................................... 235
ADDLW..................................................................... 237
ADDWF .................................................................... 237
ANDLW..................................................................... 237
ANDWF .................................................................... 237
MOVF ....................................................................... 240
BCF .......................................................................... 237
BSF........................................................................... 237
BTFSC...................................................................... 237
BTFSS ...................................................................... 238
CALL......................................................................... 238
CLRF ........................................................................ 238
CLRW ....................................................................... 238
CLRWDT .................................................................. 238
COMF ....................................................................... 238
DECF........................................................................ 238
DECFSZ ................................................................... 239
GOTO ....................................................................... 239
INCF ......................................................................... 239
INCFSZ..................................................................... 239
IORLW ...................................................................... 239
IORWF...................................................................... 239
MOVLW .................................................................... 240
MOVWF.................................................................... 240
NOP.......................................................................... 240
RETFIE..................................................................... 241
RETLW ..................................................................... 241
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DS41291G-page 327