|
PIC16F887I-PT Datasheet, PDF (239/338 Pages) Microchip Technology – 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers | |||
|
◁ |
PIC16F882/883/884/886/887
DECFSZ
Decrement f, Skip if 0
Syntax:
Operands:
Operation:
Status Affected:
Description:
[ label ] DECFSZ f,d
0 ï£ f ï£ 127
d ï [0,1]
(f) - 1 ï® (destination);
skip if result = 0
None
The contents of register âfâ are
decremented. If âdâ is â0â, the result
is placed in the W register. If âdâ is
â1â, the result is placed back in
register âfâ.
If the result is â1â, the next
instruction is executed. If the
result is â0â, then a NOP is
executed instead, making it a
two-cycle instruction.
GOTO
Unconditional Branch
Syntax:
Operands:
Operation:
Status Affected:
Description:
[ label ] GOTO k
0 ï£ k ï£ 2047
k ï® PC<10:0>
PCLATH<4:3> ï® PC<12:11>
None
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Increment f
[ label ] INCF f,d
0 ï£ f ï£ 127
d ï [0,1]
(f) + 1 ï® (destination)
Z
The contents of register âfâ are
incremented. If âdâ is â0â, the result
is placed in the W register. If âdâ is
â1â, the result is placed back in
register âfâ.
INCFSZ
Increment f, Skip if 0
Syntax:
Operands:
Operation:
Status Affected:
Description:
[ label ] INCFSZ f,d
0 ï£ f ï£ 127
d ï [0,1]
(f) + 1 ï® (destination),
skip if result = 0
None
The contents of register âfâ are
incremented. If âdâ is â0â, the result
is placed in the W register. If âdâ is
â1â, the result is placed back in
register âfâ.
If the result is â1â, the next
instruction is executed. If the
result is â0â, a NOP is executed
instead, making it a two-cycle
instruction.
IORLW
Syntax:
Operands:
Operation:
Status Affected:
Description:
Inclusive OR literal with W
[ label ] IORLW k
0 ï£ k ï£ 255
(W) .OR. k ï® (W)
Z
The contents of the W register are
ORâed with the eight-bit literal âkâ.
The result is placed in the
W register.
IORWF
Syntax:
Operands:
Operation:
Status Affected:
Description:
Inclusive OR W with f
[ label ] IORWF f,d
0 ï£ f ï£ 127
d ï [0,1]
(W) .OR. (f) ï® (destination)
Z
Inclusive OR the W register with
register âfâ. If âdâ is â0â, the result is
placed in the W register. If âdâ is
â1â, the result is placed back in
register âfâ.
ï£ 2006-2012 Microchip Technology Inc.
DS41291G-page 239
|
▷ |