EVB-LAN9252-DIG-IO Datasheet, PDF (19/37 Pages) Microchip Technology – EVB-LAN9252-DIG-IO EtherCAT® DIG I/O User’s Guide

Board Details & Configuration
2.4.6 DIG Bidirectional Mode
The DIG Bidirectional Mode can be selected by shorting the respective test point pins
with the headers J10 and J11, as detailed in Table 2-14. The input and output signal
states in this mode are the same as detailed in Section 2.4.4 “DIG INPUT Mode” and
Section 2.4.5 “DIG OUTPUT Mode”.
TABLE 2-14: DIGITAL I/O BIDIRECTIONAL MODE DESCRIPTION
Description
Short Pins
Digital I/O 0 to 7
Digital I/O 8 to 15
TP5 & J10.1, TP6 & J10.4, TP7 & J10.7, TP8 & J10.10 TP9 & J10.13,
TP10 & J10.16, TP11 & J10.19, TP12 & J10.22, TP13&J10.3,
TP14&J10.6, TP15&J10.9, TP16& J10.12, TP17&J10.15,
TP18&J10.18, TP19& J10.21, TP20&J10.24
TP21 & J11.1, TP22 & J11.4, TP23 & J11.7, TP24 & J11.10, TP25 &
J11.13, TP26 & J11.16, TP27 & J11.19, TP28 & J11.22, TP29&J11.3,
TP30&J11.6, TP31&J11.9, TP32& J11.12, TP33&J11.15,
TP34&J11.18,TP35& J11.21, TP36&J11.24
2.4.7 Control Signals
All control signals can be probed and controlled via the J12 header, as shown in
Table 2-15.
TABLE 2-15: J12 HEADER CONTROL SIGNAL MAPPING
J12 Pin Number
J12 Signal
J12 Pin Number
1
3V3
2
3
WD_STATE
4
5
EOF
6
7
SOF
8
9
LATCH0
10
11
LATCH1
12
13
WD_TRIG
14
15
OE_EXIT
16
17
OUTVALID
18
19
LATCH_IN
20
J12 Signal
3V3
GND
GND
GND
GND
GND
GND
3V3
GND
GND
Note: J12 pins 15 & 16 must be shorted in output mode.
2.4.7.1 WD_STATE
This pin is the SyncManager Watchdog State output. A “0” indicates the watchdog has
expired. The state of this signal can be seen in the LED D22.
Note: This signal is not driven (high impedance) until the EEPROM is loaded.
2.4.7.2 LATCH_IN
This pin is the external data latch signal. The input data is sampled each time a rising
edge of LATCH_IN is recognized. By default, this signals is pulled high through
R131and can be made low using switch SW6.
 2014 Microchip Technology Inc.
Preliminary
DS50002332A-page 19