EVB-LAN9252-DIG-IO Datasheet, PDF (11/37 Pages) Microchip Technology – EVB-LAN9252-DIG-IO EtherCAT® DIG I/O User’s Guide

EVB-LAN9252-DIG-IO
ETHERCAT® DIG I/O
USER’S GUIDE
Chapter 1. Overview
1.1 INTRODUCTION
The LAN9252 is a 2-port EtherCAT® slave controller with dual integrated Ethernet
PHYs which each contain a full-duplex 100BASE-TX transceiver and support 100Mbps
(100BASE-TX) operation. 100BASE-FX is supported via an external fiber transceiver.
Each port receives an EtherCAT® frame, performs frame checking and forwards it to
the next port. Time stamps of received frames are generated when they are received.
The Loop-back function of each port forwards the frames to the next logical port if there
is either no link at a port, if the port is not available, or if the loop is closed for that port.
The Loop-back function of port 0 forwards the frames to the EtherCAT® Processing
Unit. The loop settings can be controlled by the EtherCAT® master.
Packets are forwarded in the following order:
Port 0 -> EtherCAT® Processing Unit -> Port 1 -> Port 2.
The EtherCAT® Processing Unit (EPU) receives, analyzes and processes the Ether-
CAT® data stream. The main purpose of the EtherCAT® Processing unit is to enable
and coordinate access to the internal registers and the memory space of the ESC,
which can be addressed both from the EtherCAT® master and from the local applica-
tion. Data exchange between master and slave applications is comparable to a
dual-ported memory (process memory), enhanced by special functions for consistency
checking (SyncManager) and data mapping (FMMU). Each FMMU performs bitwise
mapping of logical EtherCAT® system addresses to physical device addresses.
The scope of this document is to describe the EVB-LAN9252-DIG-IO setup, which sup-
ports a Digital I/O Interface and corresponding jumper configurations. The LAN9252 is
connected to an RJ45 Ethernet jack with integrated magnetics for 100BASE-TX con-
nectivity. A simplified block diagram of the EVB-LAN9252-DIG-IO is shown in
Figure 1-1.
 2014 Microchip Technology Inc.
Preliminary
DS50002332A-page 11