EVB-LAN9252-DIG-IO Datasheet, PDF (18/37 Pages) Microchip Technology – EVB-LAN9252-DIG-IO EtherCAT® DIG I/O User’s Guide

EVB-LAN9252-DIG-IO EtherCAT® DIG I/O User’s Guide
2.4.3 EEPROM Switch
The EVB-LAN9252-DIG-IO utilizes 0x50 (7-bit) I²C slave addressing. The SW3 switch
can be used to select the A0, A1, and A2 address bits, as shown in Figure 2-2 and
Table 2-11. The eighth bit of the slave address determines if the master device wants
to read or write to the EEPROM (24C512).
FIGURE 2-2:
SLAVE ADDRESS ALLOCATION
Start
Read/Write
1 0 1 0 A2 A1 A0 R/W A
Slave Address
TABLE 2-11: EEPROM SWITCH
Switch
Description
Settings
SW3
I2C EEPROM address selection switch ON for logic 0 (default)
(A0, A1, A2). See Figure 2-2.
OFF for logic 1
2.4.4 DIG INPUT Mode
The DIG INPUT Mode can be selected through the headers J10 and J11:
• Logic 1 : (Default) SW4 & SW5 Off position. DIG I/P 0 to 15 tied to pull-up (R98 to
R113)
• Logic 0 : The respective knob of 2-way, 8-position dip switch (SW4 & SW5) need
to be moved to ON side. Signals can be selected individually.
TABLE 2-12: DIGITAL I/O INPUT MODE SELECTION
Header
Description
Short Pins
J10
Digital Input 0 to 7 1&2, 4&5, 7&8, 10&11, 13&14, 16&17, 19&20, 22&23
J11
Digital Input 8 to 15 1&2, 4&5, 7&8, 10&11, 13&14, 16&17, 19&20, 22&23
2.4.5 DIG OUTPUT Mode
The DIG OUTPUT Mode can be selected through the headers J10 and J11. The
updated Digital I/O values can be seen on the LEDs (D6 to D21):
• Logic 1 : LED illuminated
• Logic 0 : LED not illuminated.
Note: LED (D6 to D21) anode connected to ASIC.
TABLE 2-13:
Header
J10
J11
DIGITAL I/O OUTPUT MODE SELECTION (DEFAULT MODE)
Description
Short Pins
Digital I/O 0 to 7 2&3, 5&6, 8&9, 11&12, 14&15, 17&18, 20&21, 23&24
Digital I/O 8 to 15 2&3, 5&6, 8&9, 11&12, 14&15, 17&18, 20&21, 23&24
Note: The control signal OE_EXT should be connected high by shorting J12 pins
15 and 16.
DS50002332A-page 18
Preliminary
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