EVB-LAN9252-DIG-IO Datasheet, PDF (13/37 Pages) Microchip Technology – EVB-LAN9252-DIG-IO EtherCAT® DIG I/O User’s Guide

EVB-LAN9252-DIG-IO
ETHERCAT® DIG I/O
USER’S GUIDE
Chapter 2. Board Details & Configuration
This section includes sub-sections on the following EVB-LAN9252-DIG-IO details:
• Power
• Resets
• Clock
• Configuration
• Mechanicals
2.1 POWER
2.1.1 +5V Power
Power is supplied to the LAN9252 by a +3.3V on-board regulator, which is powered by
a +5V external wall adapter (Manufacturer: TRIAD MAGNETICS and P/N:
WSU050-3000). The LAN9252 includes an internal +1.2V regulator which supplies
power to the internal core logic. Assertion of the D1 Green LED indicates successful
generation of +3.3V output. The SW1 switch must be in the ON position for the +5V to
power the +3.3V regulator.
2.2 RESETS
2.2.1 Power-on Reset
A power-on reset occurs whenever power is initially applied to the LAN9252 or if the
power is removed and reapplied to the LAN9252. This event resets all circuitry within
the LAN9252. After initial power-on, the LAN9252 can be reset by pressing the reset
switch SW2. The reset LED D2 will assert (red) if when the LAN9252 is in reset condi-
tion. For stability, a delay of approximately 180ms is added from the +3.3V output to
reset release.
2.2.2 Reset Out
The LAN9252 reset pin can be configured as an output to reset the SoC. The RST# pin
becomes an open-drain output and is asserted for the minimum required time of 80ms.
2.2.3 GPIO Reset
The EVB-LAN9252-DIG-IO provides the option to reset the LAN9252 through a PIC
GPIO pin [95(RG14)]. The SW10 switch is used for this selection, as shown in
Table 2-1.
TABLE 2-1: RESET CONFIGURATION SWITCH
Switch
Short Pins Knob Position
Function
SW10 1-3
1-2
System Reset (SYS_RST) (Default)
SW10 1-2
1-3
GPIO Reset (GPIO_RST)
 2014 Microchip Technology Inc.
Preliminary
DS50002332A-page 13