PIC24HJ64GP506-I Datasheet, PDF (171/292 Pages) Microchip Technology – High-Performance, 16-Bit Microcontrollers

PIC24HJXXXGPX06/X08/X10
18.0 UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note:
This data sheet summarizes the features
of the PIC24HJXXXGPX06/X08/X10 fam-
ily of devices. However, it is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the “PIC24H Family Refer-
ence Manual”, Section 17. “UART”
(DS70232), which is available from the
Microchip website (www.microchip.com).
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in the PIC24HJXXXGPX06/X08/X10 device fam-
ily. The UART is a full-duplex asynchronous system
that can communicate with peripheral devices, such as
personal computers, LIN, RS-232 and RS-485 inter-
faces. The module also supports a hardware flow con-
trol option with the UxCTS and UxRTS pins and also
includes an IrDA^® encoder and decoder.
The primary features of the UART module are:
• Full-Duplex, 8 or 9-bit Data Transmission through
the UxTX and UxRX pins
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
• Hardware Flow Control Option with UxCTS and
UxRTS pins
• Fully Integrated Baud Rate Generator with 16-bit
Prescaler
• Baud rates ranging from 1 Mbps to 15 bps at 16x
mode at 40 MIPS
• Baud rates ranging from 4 Mbps to 61 bps at 4x mode
at 40 MIPS
• 4-deep First-In-First-Out (FIFO) Transmit Data
Buffer
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UART Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Supports Automatic Baud Rate Detection
• IrDA^® Encoder and Decoder Logic
• 16x Baud Clock Output for IrDA^® Support
A simplified block diagram of the UART is shown in
Figure 18-1. The UART module consists of the key
important hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA^®
BCLK
Hardware Flow Control
UART Receiver
UxRTS
UxCTS
UxRX
UART Transmitter
UxTX
Note 1: Both UART1 and UART2 can trigger a DMA data transfer. If U1TX, U1RX, U2TX or U2RX is selected as
a DMA IRQ source, a DMA transfer occurs when the U1TXIF, U1RXIF, U2TXIF or U2RXIF bit gets set as
a result of a UART1 or UART2 transmission or reception.
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word
(i.e., UTXISEL<1:0> = 00 and URXISEL<1:0> = 00).
© 2009 Microchip Technology Inc.
DS70175H-page 169