DSPIC30F6011_06 Datasheet, PDF (141/228 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F6011/6012/6013/6014
The following figure depicts the recommended circuit
for the conversion rates above 200 ksps. The
dsPIC30F6014 is shown as an example.
FIGURE 19-2:
ADC VOLTAGE REFERENCE SCHEMATIC
VDD
VDD
VDD
R2
10
C2
0.1 μF
1
2
3
4
5
6
7
8
9
10
VSS
VDD
13
14
15
16
17
18
19
20
C1
R1
0.01 μF 10
dsPIC30F6014
60
59
58
57
See Note 1:
56
55
VDD
VDD
VDD
54
53
C8
C7
C6
1 μF
0.1 μF 0.01 μF
52
VSS
50
49
VDD
VDD
47
46
AVDD
AVDD
AVDD
45
C5
C4
C3
44
1 μF
0.1 μF 0.01 μF
43
42
41
VDD
VDD
Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.
The configuration procedures below give the required
setup values for the conversion speeds above 100
ksps.
19.7.1 200 KSPS CONFIGURATION
GUIDELINE
The following configuration items are required to
achieve a 200 ksps conversion rate.
• Comply with conditions provided in Table 19-2.
• Connect external VREF+ and VREF- pins following
the recommended circuit shown in Figure 19-2.
• Set SSRC<2.0> = 111 in the ADCON1 register to
enable the auto convert option.
• Enable automatic sampling by setting the ASAM
control bit in the ADCON1 register.
• Write the SMPI<3.0> control bits in the ADCON2
register for the desired number of conversions
between interrupts.
• Configure the ADC clock period to be:
1
= 334 ns
(14 + 1) x 200,000
by writing to the ADCS<5:0> control bits in the
ADCON3 register.
• Configure the sampling time to be 1 TAD by
writing: SAMC<4:0> = 00001.
The following figure shows the timing diagram of the
ADC running at 200 ksps. The TAD selection in conjunc-
tion with the guidelines described above allows a con-
version speed of 200 ksps. See Example 19-1 for code
example.
© 2006 Microchip Technology Inc.
DS70117F-page 139