DSPIC30F6011_06 Datasheet, PDF (130/228 Pages) Microchip Technology – High-Performance, 16-Bit Digital Signal Controllers

dsPIC30F6011/6012/6013/6014
18.3.6 SLAVE FRAME SYNC OPERATION
When the DCI module is operating as a frame sync
slave (COFSD = 1), data transfers are controlled by the
Codec device attached to the DCI module. The
COFSM control bits control how the DCI module
responds to incoming COFS signals.
In the Multi-Channel mode, a new data frame transfer
will begin one CSCK cycle after the COFS pin is sam-
pled high (see Figure 18-2). The pulse on the COFS
pin resets the frame sync generator logic.
In the I²S mode, a new data word will be transferred
one CSCK cycle after a low-to-high or a high-to-low
transition is sampled on the COFS pin. A rising or fall-
ing edge on the COFS pin resets the frame sync
generator logic.
In the AC-Link mode, the tag slot and subsequent data
slots for the next frame will be transferred one CSCK
cycle after the COFS pin is sampled high.
The COFSG and WS bits must be configured to pro-
vide the proper frame length when the module is oper-
ating in the Slave mode. Once a valid frame sync pulse
has been sampled by the module on the COFS pin, an
entire data frame transfer will take place. The module
will not respond to further frame sync pulses until the
data frame transfer has completed.
FIGURE 18-2:
FRAME SYNC TIMING, MULTI-CHANNEL MODE
CSCK
COFS
CSDI/CSDO
MSB
LSB
FIGURE 18-3:
FRAME SYNC TIMING, AC-LINK START OF FRAME
BIT_CLK
CSDO or CSDI
SYNC
S12 S12 S12 Tag Tag Tag
bit 2 bit 1 LSb MSb bit 14 bit 13
FIGURE 18-4:
I²S INTERFACE FRAME SYNC TIMING
CSCK
CSDI or CSDO
MSB
LSB MSB
LSB
WS
Note:
A 5-bit transfer is shown here for illustration purposes. The I²S protocol does not specify word length – this
will be system dependent.
DS70117F-page 128
© 2006 Microchip Technology Inc.