PIC16F684_07 Datasheet, PDF (115/192 Pages) Microchip Technology – 14-Pin, Flash-Based 8-Bit CMOS Microcontrollers with nanoWatt Technology

PIC16F684
FIGURE 12-10: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
CLKOUT⁽⁴⁾
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
TOST⁽²⁾
INT pin
INTF flag
(INTCON reg.)
Interrupt Latency⁽³⁾
GIE bit
(INTCON reg.)
Processor in
Sleep
Instruction Flow
PC
PC
Instruction
Fetched
Inst(PC) = Sleep
Instruction
Executed
Inst(PC – 1)
PC + 1
Inst(PC + 1)
Sleep
PC + 2
PC + 2
Inst(PC + 2)
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
Inst(0004h)
Dummy Cycle
0005h
Inst(0005h)
Inst(0004h)
Note 1:
2:
3:
4:
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale). This delay does not apply to EC, INTOSC and RC Oscillator modes.
GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
12.8 Code Protection
If the code protection bit(s) have not been
programmed, the on-chip program memory can be
read out using ICSP^™ for verification purposes.
Note:
The entire data EEPROM and Flash pro-
gram memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory
Programming Specification” (DS41204)
for more information.
12.9 ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
© 2007 Microchip Technology Inc.
DS41202F-page 113