KSZ8841-16_08 Datasheet, PDF (91/105 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel, Inc.
Asynchronous Timing using DATACSN
KSZ8841-16/32 MQL/MVL/MBL
DATACSN
Read Data
RDN, WRN
Write Data
ARDY
(Read Cycle)
ARDY
(Write Cycle)
t2
t1
t7
valid
t5
t4
t6
valid
t3
t9
t8
t10
Figure 15. Asynchronous Cycle – Using DATACSN
Symbol Parameter
Min Typ Max Unit
t1
DATACSN setup to RDN, WRN active
2
ns
t2
DATACSN hold after RDN, WRN inactive (assume 0
ns
ADSN tied Low)
t3
Read data hold to ARDY rising
0.8
ns
t4
Read data to RDN hold
4
ns
t5
Write data setup to WRN inactive
4
ns
t6
Write data hold after WRN inactive
2
ns
t7
Read active to ARDY Low
8
ns
t8
Write inactive to ARDY Low
8
ns
t9
ARDY low (wait time) in read cycle (Note1)
0
40
ns
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
ARDY low (wait time) in read cycle (Note1)
0
80
ns
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
t10
ARDY low (wait time) in write cycle (Note1)
0
50
ns
(It is 0ns to write bank select register)
(It is 36ns to write QMU data register)
Table 18. Asynchronous Cycle using DATACSN Timing Parameters
Notes:
1. When CPU finished current Read or Write operation, it can do next Read or Write operation even the ARDY is low. During Read or
Write operation if the ADRY is low, the CPU has to keep the RDN/WRN low until the ARDY returns to high.
2. In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only supported in the A6
device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
October 2007
91
M9999-102207-1.6