KSZ8841-16_08 Datasheet, PDF (33/105 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
control is based on availability of the system resources.
The KSZ8841M issues a flow control frame (Xoff, or transmitter off), containing the maximum pause time defined in IEEE
standard 802.3x. Once the resource is freed up, the KSZ8841M sends out the another flow control frame (Xon, or
transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is
provided to prevent the flow control mechanism from being constantly activated and deactivated.
Half-Duplex Backpressure
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation
conditions are the same as in full-duplex mode. If backpressure is required, the KSZ8841M sends preambles to defer the
other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8841M
discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other
stations from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are
transmitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until
chip resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is
generated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet
reception.
Clock Generator
The X1 and X2 pins are connected to a 25MHz crystal. X1 can also serve as the connector to a 3.3V, 25MHz oscillator
(as described in the pin description).
The bus interface unit (BIU) uses BCLK (Bus Clock) for synchronous accesses. The maximum frequency is 50MHz for
VLBus-like and EISA-like slave direct memory access (DMA).
Bus Interface Unit (BIU)
The BIU host interface is a generic bus interface, designed to communicate with embedded processors. The use of glue
logic may be required when it talks to various standard buses and processors.
Supported Transfers
In terms of transfer type, the BIU can support two transfers: asynchronous transfer and synchronous transfer. To support
these transfers (asynchronous and synchronous), the BIU provides three groups of signals:
Synchronous signals
Asynchronous signals
Common signals are used for both synchronous and asynchronous transfers.
Since both synchronous and asynchronous signals are independent of each other, synchronous transfer and
asynchronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of common signals).
Physical Data Bus Size
The BIU supports an 8-bit, 16-bit, or 32-bit host standard data bus. Depending on the size of the physical data bus, the
KSZ8841M supports 8-bit, 16-bit, or 32-bit data transfers
For example,
For a 32-bit system/host data bus, the KSZ8841M allows an 8-bit, 16-bit, and 32-bit data transfer (KSZ8841-32MQL).
For a 16-bit system/host data bus, the KSZ8841M allows an 8-bit and 16-bit data transfer (KSZ8841-16MQL).
For an 8-bit system/host data bus, the KSZ8841M only allows an 8-bit data transfer (KSZ8841-16MQL).
The KSZ8841M does not support internal data byte-swap but it does support internal data word-swap. This means that
the system/host data bus HD[7:0] must connect to both D[7:0] and D[15:8] for an 8-bit data bus interface. For a 16-bit data
bus, the system/host data bus HD[15:8] and HD[7:0] only need to connect to D[15:8] and D[7:0] respectively, and there is
no need to connect HD[15:8] and HD[7:0] to D[31:24] and D[23:16].
Table 2 describes the BIU signal grouping.
October 2007
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