KSZ8841-16_08 Datasheet, PDF (64/105 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value R/W Description
15-11 -
RO Reserved.
10
0x0
RW RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8841M is in full-duplex mode, flow control is enabled, and the
KSZ8841M will acknowledge a PAUSE frame from the receive interface; i.e., the outgoing
packets are pending in the transmit buffer until the PAUSE frame control timer expires. This
field has no meaning in half-duplex mode and should be programmed to 0.
When this bit is cleared, flow control is not enabled.
9
0x0
RW RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue.
When this bit is cleared, all CRC error frames are discarded.
8
-
RO Reserved.
7
0x0
RW RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
6
0x0
RW RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
5
0x0
RW RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit Station MAC
address of the module.
4
0x0
RW RXRA Receive All
When this bit is set, the KSZ8841M receives all incoming frames, regardless of the frame’s
destination address.
3
0x0
RW RXSCE Receive Strip CRC
When this bit is set, the KSZ8841M strips the CRC on the received frames. Once cleared, the
CRC is stored in memory following the packet.
2
0x0
RW QMU Receive Multicast Hash-Table Enable
When this bit is set, this bit enables the RX function to receive multicast frames that pass the
CRC Hash filtering mechanism.
1
-
RO Reserved.
0
0x0
RW RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state.
When this bit is cleared, the receive process is placed in the stopped state upon completing
reception of the current frame.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit
Default Value R/W Description
15-13 -
RO Reserved.
12-0
-
RO TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is used for
both frame payload, control word.
Note: Software must be written to ensure that there is enough memory for the next transmit
frame including control information before transmit data is written to the TXQ.
October 2007
64
M9999-102207-1.6