KSZ8841-16_08 Datasheet, PDF (73/105 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Bit
Default Value R/W Description
3
0
RO
No Soft Reset
If this bit is set (“1”), the KSZ8841M does not perform an internal reset when transitioning from
D3_hot to D0 because of PowerState commands. Configuration context is preserved. Upon
transition from D3_hot to the D0 Initialized state, no additional operating system intervention is
required to preserve configuration context beyond writing the PowerState bits.
If this bit is cleared (“0”), the KSZ8841M does perform an internal reset when transitioning
from D3_hot to D0 via software control of the PowerState bits. Configuration context is lost
when performing the soft reset. Upon transition from D3_hot to the D0 state, full reinitialization
sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3_hot to D0 by a system or bus segment
reset will return to the device state D0 Uninitialized with only PME context preserved if PME is
supported and enabled.
The value of this bit is loaded from the NO_SRST bit in the serial EEPROM.
2
0
RO
Reserved.
1-0
0x0
RW Power State
This field is used to set the new power state of the KSZ8841M as well as to determine its
current power state. The definitions of the field values are:
00: D0 -> System is on and running
01: D1 -> Low-power state
10: D2 -> Low-power state
11: D3 (hot) -> System is off and not running
Banks 20 – 31: Reserved
Except Bank Select Register (0xE).
Bank 32 Chip ID and Enable Register (0x00): CIDER
This register contains the chip ID and the chip enable bit.
Bit
Default
R/W Description
15-8
7-4
3-1
0
0x88
0x1
0x1
0
RO Family ID
Chip family ID
RO Chip ID
0x1 is assigned to KSZ8841M
RO Revision ID
RO Reserved.
October 2007
73
M9999-102207-1.6