KSZ8841-16_08 Datasheet, PDF (68/105 Pages) Micrel Semiconductor – Single-Port Ethernet MAC Controller with Non-PCI Interface

Micrel, Inc.
KSZ8841-16/32 MQL/MVL/MBL
Bank 18 Interrupt Enable Register (0x00): IER
This register enables the interrupts from the QMU and other sources.
Bit
Default Value R/W Description
15
0x0
RW LCIE Link Change Interrupt Enable
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
14
0x0
RW TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
13
0x0
RW RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
12
0x0
RW TXUIE Transmit Underrun Interrupt Enable
When this bit is set, the transmit underrun interrupt is enabled.
When this bit is reset, the transmit underrun interrupt is disabled.
11
0x0
RW RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
10
0x0
RW RXEIE Receive Early Receive Interrupt Enable
When this bit is set, the Early Receive interrupt is enabled.
When this bit is reset, the Early Receive interrupt is disabled.
9
0x0
RW TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is enabled.
When this bit is reset, the Transmit Process Stopped interrupt is disabled.
8
0x0
RW RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is enabled.
When this bit is reset, the Receive Process Stopped interrupt is disabled.
7
0x0
RW RXEFIE Receive Error Frame Interrupt Enable
When this bit is set, the Receive error frame interrupt is enabled.
When this bit is reset, the Receive error frame interrupt is disabled.
6-0
-
RO Reserved.
October 2007
68
M9999-102207-1.6