KSZ8895MLU_11 Datasheet, PDF(87/110 Page) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Switch

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

KSZ8895MLU_11 Datasheet, PDF (87/110 Pages) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Switch

◁

Micrel, Inc.

KSZ8895MLU

In order to read one VLAN entry, the VLAN set is read first and the specific VLAN entry information can be extracted. To

update any VLAN entry, the VLAN set is read first then only the desired VLAN entry is updated and the whole VLAN set is

written back. Due to FID in VLAN table is 7-bit, so the VLAN table supports unique 128 flow VLAN groups. Each VLAN set

address is 10 bits long (Maximum is 1024) in the indirect address register 110 and 111, the bit [9 ï 8] of VLAN set

address is at bit [1 ï 0] of register 110, and the bit [7 ï 0] of VLAN set address is at bit [7-0] of register 111. Each Write

and Read can access to four consecutive VLAN entries.

Examples:

(1) VLAN Table Read (read the VID=2 entry)

Write the indirect control and address registers first

Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)

Write to Register 111 (0x6F) with 0x0 (trigger the read operation for VID=0, 1, 2, 3 entries)

Then read the indirect data registers bits [38-26] for VID=2 entry

Read Register 116 (0x74), (register116[6:0] are bits 12 ï 6 of VLAN VID=2 entry)

Read Register 117 (0x75), (register117[7:2] are bits 5 ï 0 of VLAN VID=2 entry)

(2) VLAN Table Write (write the VID=10 entry)

Read the VLAN set that contains VID=8, 9, 10, 11.

Write to Register 110 (0x6E) with 0x14 (read VLAN table selected)

Write to Register 111 (0x6F) with 0x02 (trigger the read operation and VID=8, 9, 10, 11 indirect address)

Read the VLAN set first by the indirect data registers 114, 115, 116, 117, 118, 119, 120.

Modify the indirect data registers bits [38 ï 26] by the register 116 bit [6-0] and register 117 bit [7 ï 2] as follows:

Write to Register 116 (0x74), (register116[6:0] are bits 12 ï 6 of VLAN VID=10 entry)

Write to Register 117 (0x75), (register117[7:2] are bits 5 ï 0 of VLAN VID=10 entry)

Then write the indirect control and address registers

Write to Register 110 (0x6E) with 0x04 (write VLAN table selected)

Write to Register 111 (0x6F) with 0x02 (trigger the write operation and VID=8, 9, 10, 11 indirect address)

Table 14 shows the relationship of the indirect address/data registers and VLAN ID.

October 2011

M9999-100311-1.1

▷