KSZ8895MLU_11 Datasheet, PDF (79/110 Pages) Micrel Semiconductor – Integrated 5-Port 10/100 Managed Switch

Micrel, Inc.
KSZ8895MLU
Advanced Control Registers (Continued)
Register 183 (0xB7): Port 1 Priority 0 Ingress Limit Control 1
Register 199 (0xC7): Port 2 Priority 0 Ingress Limit Control 1
Register 215 (0xD7): Port 3 Priority 0 Ingress Limit Control 1
Register 231 (0xE7): Port 4 Priority 0 Ingress Limit Control 1
Register 247 (0xF7): Port 5 Priority 0 Ingress Limit Control 1
Address Name
Description
7
Reserved
60
Port-Based Priority 0 Ingress
Limit
Ingress data rate limit for priority 0 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
Register 184 (0xB8): Port 1 Priority 1 Ingress Limit Control 2
Register 200 (0xC8): Port 2 Priority 1 Ingress Limit Control 2
Register 216 (0xD8): Port 3 Priority 1 Ingress Limit Control 2
Register 232 (0xE8): Port 4 Priority 1 Ingress Limit Control 2
Register 248 (0xF8): Port 5 Priority 1 Ingress Limit Control 2
Address Name
Description
7
Reserved
60
Port-Based Priority 1 Ingress
Limit
Ingress data rate limit for priority 1 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
Register 185 (0xB9): Port 1 Priority 2 Ingress Limit Control 3
Register 201 (0xC9): Port 2 Priority 2 Ingress Limit Control 3
Register 217 (0xD9): Port 3 Priority 2 Ingress Limit Control 3
Register 233 (0xE9): Port 4 Priority 2 Ingress Limit Control 3
Register 249 (0xF9): Port 5 Priority 2 Ingress Limit Control 3
Address Name
Description
7
Reserved
60
Port-Based Priority 2 Ingress
Limit
Ingress data rate limit for priority 2 frames
Ingress traffic from this port is shaped according to the
Data Rate Selected Table. See the table follow the
end of Egress limit control registers
Mode
RO
R/W
Mode
RO
R/W
Mode
RO
R/W
Default
0
0000000
Default
0
0000000
Default
0
0000000
October 2011
79
M9999-100311-1.1