MIC3003 Datasheet, PDF (8/75 Pages) Micrel Semiconductor – FOM Management IC with Internal Calibration

Micrel, Inc.
Pin Configuration
MIC3003
24-Pin MLF^® (MLF-24)
Pin Description
Pin Number
1
Pin Name
FB
2
VMPD
3
GNDA
4
VDDA
5
VILD–
6
VILD+
7
SHDN/TXFIN
8
VRX
9
RS1
10
TXFAULT
Pin Function
Analog Input. Feedback voltage for the APC loop op-amp. Polarity and scale are programmable
via the APC configuration bits I OEMCFG1. Connect to V_BIAS if APC is not used.
Analog Input. Multiplexed A/D converter input for monitoring transmitted optical power via a
monitor photodiode. In most applications, VMPD will be connected directly to FB. The input range
is 0 - V_REF or 0 - V_REF/4 depending upon the setting of the APC configuration bits
Ground return for analog functions.
Power supply input for analog functions.
Analog Input. Reference terminal for the multiplexed pseudo-differential A/D converter inputs for
monitoring laser bias current via a sense resistor (VILD+ is the sensing input). Tie to V_DD or GND
to reference the voltage sensed on VILD+ to V_DD or GND, respectively.
Analog Input. Multiplexed A/D input for monitoring laser bias current via a sense resistor (signal
input); accommodates inputs referenced to V_DD or GND (see pin 5 description).
Digital output/Input; programmable polarity. When used as shutdown output (SHDN), OEMCFG3
bit 2 set to 0, SHDN is asserted at the detection of a fault condition if OEMCFG4 bit 7 is set to 0. If
OEMCFG4 bit 7 is set to 1, a fault condition will not assert SHDN. When programmed as TXFIN, it
is an input for external fault signals to be ORed with the internal fault sources to drive TXFAULT.
Analog Input. Multiplexed A/D converter input for monitoring received optical power. The input
range is 0 to V_REF. A 5-bit programmable EEPOT on this pin provides coarse calibration and
ranging of the RX power measurement.
Digital Input; Transmitter Rate Select Input; ORed with soft rate select bit SRS1 to determine the
state of the TRSOUT pin. The state of this pin is always reflected in the RS1S bit.
Digital Output; Open-Drain, with programmable polarity. If OEMCFG5 bit 4 is set to 0, a high level
indicates a hardware fault impeding transmitter operation. If OEMCFG5 bit 4 is set to 1, a low level
indicates a hardware fault impeding transmitter operation. The state of this pin is always reflected
in the TXFLT bit.
November 2009
8
M9999-111209-C
[e-mail] or [phone]