MIC3003 Datasheet, PDF (13/75 Pages) Micrel Semiconductor – FOM Management IC with Internal Calibration

Micrel, Inc.
MIC3003
Electrical Characteristics
Symbol
Parameter
Condition
Min Typ Max Units
Control and Status I/O Timing, TXFAULT, TXDISABLE, RS0, RRSOUT, and RXLOS
tOFF
tON
tINIT
TXDISABLE Assert Time
TXDISABLE De-assert Time
Initialization Time
From input asserted to optical output
at 10% of nominal, C_COMP = 10nF.
From input de-asserted to optical output
at 90% of nominal, C_COMP = 10nF.
From power on or transmitter enabled to
optical output at 90% of nominal and
TX_FAULT de-asserted. Note 10
tINIT2
Power-on Initialization Time
From power on to APC loop-enabled.
tFAULT
TXFAULT Assert Time
From fault condition to TXFAULT
assertion. Note 10
tRESET
Fault Reset Time
Length of time TXDISABLE must be
10
asserted to reset fault condition.
tLOSS_ON RXLOS Assert Time
From loss of signal to RXLOS asserted.
tLOSS_OFF RXLOS De-assert Time
From signal acquisition to LOS
de-asserted.
tDATA
Analog Parameter Data Ready
From power on to valid analog
parameter data available. Note 10
tPROP_IN
TXFAULT, TXDISABLE, RXLOS,
RS0, RS1 Input Propagation Time
Time from input change to
corresponding internal register bit set or
cleared. Note 10
tPROP_OUT TXFAULT, TRSOUT, TRRSOUT,
/INT, QGPO Output Propagation
Time
From an internal register bit set or
cleared to corresponding output change.
Note 10
10
µs
1
ms
300 ms
200 ms
95
µs
µs
95
µs
100
µs
400 ms
1
µs
1
µs
Fault Comparators
FLTTMR
Fault Suppression Timer Clock
Period
Accuracy
tREJECT
Glitch Rejection
VSAT
Saturation Detection Threshold
Note 10
Maximum length pulse that will not
cause output to change state. Note 10
High level
Low level
0.475 0.5 0.525 ms
-3
+3 %/fs
4.5
µs
95
%VDDA
5
%VDDA
Power-On Hour Meter
Timebase Accuracy
Resolution
0°C ≤ T_A ≤ +70°, Note 10
–40°C ≤ T_A ≤ +105°C
Note 10
+5
-5
%
+10
-10
%
10
hours
Non-Volatile (FLASH) Memory
t_WR
Write Cycle Time, Note 11
Endurance
NVRAM Data Retention
Maximum permitted number of write
cycles to any single NVRAM location
Measured from the SMBus STOP
condition of a one-byte to eight-byte
write transaction. Note 10
100
10,000
13
ms
years
cycles
Notes:
10. Guaranteed by design and/or testing of related parameters. Not 100% tested in production.
11. The MIC3003 will not respond to serial bus transactions during an EEPROM write cycle. The host will receive a NACK response during t_WR.
November 2009
13
M9999-111209-C
[e-mail] or [phone]