PL123E-09 Datasheet, PDF (6/10 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
3.3V AND 2.5V AC ELECTRICAL SPECIFICATIONS
Description
Parameter Test Conditions
Min Typ Max Unit
3.3V High Drive
10 – 220 MHz
Maximum Frequency^[7]
(Input/Output)
3.3V Standard Drive
1/t₁
2.5V High Drive
10 – 167 MHz
10 – 200 MHz
2.5V Standard Drive
10 – 134 MHz
Input Duty Cycle
(PLL Mode only)
<133.3 MHz
T _IDC
>133.3 MHz
25 – 75 %
40 – 60 %
Output Duty Cycle^[8]
t₂ ÷ t₁
<133.3 MHz
>133.3 MHz
47 – 53 %
45 – 55 %
Standard Drive, CL = 30 pF, <100 MHz
– 1.6 – ns
Standard Drive, CL = 22 pF, <133.3 MHz – 1.6 – ns
Rise, Fall Time (3.3V)^[8]
Standard Drive, CL = 15 pF, <167 MHz
t₃,t₄
High Drive, CL = 30 pF, <100 MHz
– 0.6 – ns
– 1.2 – ns
High Drive, CL = 22 pF, <133.3 MHz
– 1.2 – ns
High Drive, CL = 15 pF, >133.3 MHz
– 0.5 – ns
Standard Drive, CL = 15 pF, <133.33 MHz – 1.5 – ns
Rise, Fall Time (2.5V)^[8]
High Drive, CL = 30 pF, <100 MHz
t₃, t₄
High Drive, CL = 22 pF, <133.3 MHz
– 2.1 – ns
– 1.3 – ns
High Drive, CL = 15 pF, >133.3 MHz
– 1.2 – ns
Output to Output Skew ^[8]
t₅
All outputs equally loaded
–
– 100 ps
Delay, REF Rising Edge
to CLKOUT Rising Edge^[8]
t₆
PLL enabled @ 3.3V
PLL enabled @2.5V
–100 –
–200 –
100 ps
200 ps
Part to Part Skew^[8]
PLL Lock Time^[8]
Cycle-to-Cycle Jitter,
Peak^{[8, 9]}
Measured at V_DD/2.
Any output to any output, 3.3V supply
t₇
Measured at V_DD/2.
Any output to any output, 2.5V supply
–
– ±150 ps
–
– ±300 ps
t_LOCK
Stable power supply, valid clocks pre-
sented on REF and CLKOUT pins
–
– 1.0 ms
3.3V, >66 MHz, <15 pF
–
– 55 ps
3.3V, >66 MHz, <30 pF, Standard. Drive
–
– 125 ps
3.3V, >66 MHz, <30 pF, High Drive
–
– 100 ps
T_JCC
2.5V, >66 MHz, <15 pF, Standard. Drive
–
– 95 ps
2.5V, >66 MHz, <15 pF, High Drive
–
– 65 ps
2.5V, >66 MHz, <30 pF, High Drive
–
– 145 ps
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 12/13/11 Page 6