PL123E-09 Datasheet, PDF (2/10 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

(Preliminary) PL123E-09
PIN DESCRIPTIONS
Low Skew Zero Delay Buffer
Name
REF^[1]
CLKA1^[2]
CLKA2^[2]
VDD
GND
CLKB1^[2]
CLKB2^[2]
S2^{[3 ]}
S1^{[3 ]}
CLKB3^[2]
CLKB4^[2]
CLKA3^[2]
CLKA4^[2]
CLKOUT ^{[2 ]}
Package Type
TSSOP-16L
SOP-16L
1
1
2
2
3
3
4,13
4,13
5,12
5,12
6
6
7
7
8
8
9
9
10
10
11
11
14
14
15
15
16
16
Type
Description
I Input reference frequency.
O Buffered clock output, Bank A
O Buffered clock output, Bank A
P VDD connection
P GND connection
O Buffered clock output, Bank B
O Buffered clock output, Bank B
I Selector input
I Selector input
O Buffered clock output, Bank B
O Buffered clock output, Bank B
O Buffered clock output, Bank A
O Buffered clock output, Bank A
O Buffered clock output. Internal feedback on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs. 3: Weak Pull-Up on S1 and S2
SELECTOR DEFINITION
S2
S1
CLOCK A1–A4
(Bank A)
0
0
Three-state
0
1
Driven
1
0
Driven
1
1
Driven
CLOCK B1–B4
(Bank B)
Three-state
Three-state
Driven
Driven
CLKOUT
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
INPUT / OUTPUT SKEW CONTROL
The PL123E-09 will achieve Zero Delay from input to output when all the outputs are loaded equally . Adjust-
ments to the input/output delay can be made by adding additional loading to the CLKOUT pin.
Please contact Micrel for more information.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 12/13/11 Page 2