PL123E-09 Datasheet, PDF (1/10 Pages) Micrel Semiconductor – Low Skew Zero Delay Buffer

FE AT UR E S
 Frequency Range 10MHz to 220MHz
 Zero input - output delay.
 Low Output to Output Skew
 Optional Drive Strength:
Standard (8mA) PL123E-09
High (12mA) PL123E-09H
 2.5V or 3.3V, ±10% operation.
 Available in 16-Pin SOP or TSSOP packages
(Preliminary) PL123E-09
Low Skew Zero Delay Buffer
DESCRIPTION
The PL123E-09 (-09H for High Drive) is a high perfor-
mance, low skew, low jitter zero delay buffer designed
to distribute high speed clocks. It has two low-skew
output banks, of 4 outputs each, that are synchronized
with the input. Control of the two banks of outputs is
achieved by using the S1 and S2 inputs as shown in
the Selector Definition table on page 2.
The synchronization is established via CLKOUT feed
back to the input of the PLL. Since the skew between
the input and output is less than 100ps, the device
acts as a zero delay buffer. The input output propaga-
tion delay can be advanced or delayed by adjusting the
load on the CLKOUT pin.
These parts are not intended for 5V input-tolerant ap-
plications.
BLOCK DIAGRAM
REF
PLL
Mux
S1
Selector
S2
Inputs
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKB1
CLKB2
CLKB3
CLKB4
REF 1
CLKA1 2
CLKA2 3
VDD 4
GND 5
CLKB1 6
CLKB2 7
S2 8
16 CLKOUT
15 CLKA4
14 CLKA3
13 VDD
12 GND
11 CLKB4
10 CLKB3
9 S1
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel [phone] • fax [phone] • www.micrel.com Rev 12/13/11 Page 1