MIC3003GFL Datasheet, PDF (57/74 Pages) Micrel Semiconductor – FOM Management IC with Internal Calibration

Micrel, Inc.
MIC3003GFL
OEM Configuration Register 2 (OEMCFG2)
D[7]
SMBADR[3]
read/write
Default value
D[6]
SMBADR[2]
read/write
Serial address
D[5]
SMBADR[1]
read/write
D[4]
SMBADR[0]
read/write
D[3]
read/write
D[2]
D[1]
D[0]
TRSTCLR[2] TRSTCLR[1] TRSTCLR[0]
read/write read/write read/write
1010 0010b = xxh (device address = 1010 xxxxb)
This value is the basis for using A0 _h, A2 _h, A4 _h, and A6 _h as the names of
the different device address spaces of the MIC3003.
A6h
Byte address
2 = 02h
Caution: Changes to SMBADR take effect immediately. Any accesses following a write to SMBADR must be to the newly
programmed serial bus address.
A valid OEM password is required for access to this register. This register is non-volatile and will be maintained through power
and reset cycles.
D[7:4]
D[3:0]
Bit(s)
SMBADR[3:0]
TRSTCLR[2:0]
Function
Most significant four bits of the
serial bus device address
Set the delay between QGPO and
the clearing of RESETOUT
Operation
Writes take effect immediately.
These three bits set the delay between the de-assertion
edge of the QGPO output in Reset mode and the
subsequent clearing of the three RESETOUT bits in the
RESETOUT Register:
000: Zero delay
001: 17.5 ms typical
010: 22.5 ms typical (default)
011: 27.0 ms typical
100: 45 ms typical
Minimum and maximum values may be found by adding
tolerances of -10% and +10% to the above values.
If Reset mode is not selected, these bits have no function.
July 2010
57
M9999-072910-A
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