MIC4102_11 Datasheet, PDF (9/17 Pages) MIC GROUP RECTIFIERS – 100V Half Bridge MOSFET Driver with Anti-Shoot Through Protection PRELIMINARY SPECIFICATIONS

Micrel, Inc.
Functional Diagram
PWM
5
V_DD
1
LS
6
VSS
7
UVLO
UVLO
MIC4102
LEVEL
SHIFT
LEVEL
SHIFT
HV
HB
2
DRIVER
HO
3
HS
4
LO
8
DRIVER
Figure 1. MIC4102 Functional Block Diagram
Functional Description
The MIC4102 is a high voltage, non-inverting,
synchronous MOSFET driver that uses a single PWM
input signal to alternately drive both high-side and low-
side N-Channel MOSFETs. The block diagram of the
MIC4102 is shown in Figure 1.
The MIC4102 input is TTL compatible. The high-side
output buffer includes a high speed level-shifting circuit
that is referenced to the HS pin. An internal diode is
used as part of a bootstrap circuit to provide the drive
voltage for the high-side output.
Startup and UVLO
The UVLO circuit forces both driver outputs low until the
supply voltage exceeds the UVLO threshold. The low-
side UVLO circuit monitors the voltage between the VDD
and VSS pins. The high-side UVLO circuit monitors the
voltage between the HB and HS pins. Hysteresis in the
UVLO circuit prevents noise and finite circuit impedance
from causing chatter during turn-on.
The VDD pin voltage is supplied to the HS pin through
the internal bootstrap diode. The HB pin voltage will
always be a diode drop less than VDD.
Input Stage
The MIC4102 utilizes a TTL compatible input stage. The
PWM input pin is referenced to the VSS pin. The
voltage state of the input signal does not change the
quiescent current draw of the driver. The threshold level
is independent of the VDD supply voltage and there is
no dependence between I_VDD and the input signal
amplitude. This feature makes the MIC4102 an
excellent level translator that will drive high threshold
MOSFETs from a low voltage PWM IC.
Low-Side Driver
A block diagram of the low-side driver is shown in Figure
2. The low-side driver is designed to drive a ground
(Vss pin) referenced N-channel MOSFET. Low driver
impedances allow the external MOSFET to be turned on
and off quickly. The rail-to-rail drive capability of the
output ensures a low Rdson from the external MOSFET.
A low level applied to PWM pin will cause the HO output
to go low and the LO output to go high. The upper driver
FET turns on and Vdd is applied to the gate of the
external MOSFET. A high level on the PWM pin forces
the LO output low by turning off the upper driver and
turning on the lower driver which ground the gate of the
external MOSFET.
Pulling the LS pin low disables the LO pin.
November 2006
9
M9999-112806