MG84FL54BD Datasheet, PDF (98/113 Pages) Megawin Technology Co., Ltd – Four and half configurable I/O ports

TXCNT (Transmit FIFO Byte Count Register, Endpoint-Indexed, Address=F6H, SYS/USB_reset=xxxx-xxxx,
Write-only)
7
6
5
4
3
2
1
0
-
TXBC6 TXBC5 TXBC4 TXBC3 TXBC2 TXBC1 TXBC0
Bit6~0: TXBC[6:0]-- Transmit Byte Count.
Stored the byte count for the data packet in the transmit FIFO specified by EPINDEX.
SIOCTL (Serial I/O Control Register, Address=C2H, SYS_RESET=xxxx-xxxx, Read-only)
7
6
5
4
3
2
1
0
DPI
DMI
-
-
-
-
-
-
Bit7: DPI-- USB DP port state, read only.
Read the port status on USB DP.
Bit6: DMI-- USB DM port state, read only.
Read the port status on USB DM.
Bit5~0: Reserved.
ACKCTL (Auxiliary Clock Register, Address=CCH, SYS_RESET=0000-0000, Read/Write)
7
6
5
4
3
2
1
0
-
-
-
-
-
-
UCK_SEL EN_CKM
Bit7~2: Reserved, always write 0.
Bit1: UCK_SEL-- USB Clock Source Selection.
Set this bit to select 48MHz clock source comes from CKM.
Clear this bit to select 48MHz clock source comes from PLL. Default is cleared.
Bit0: EN_CKM-- 4X Clock Multiplier enable bit.
If this bit is set, enable the 4X clock multiplier.
If this bit is cleared, disable the 4X clock multiplier. Default is cleared.
Note:
If using CKM to be 48MHz clock source, the OSCin must be 12MHz.
98
MG84FL54B Data Sheet
MEGAWIN