MG84FL54BD Datasheet, PDF (18/113 Pages) Megawin Technology Co., Ltd – Four and half configurable I/O ports

6.2. The Standard 8051 SFRs
The standard 80C51 SFRs are shown in Table 6-3. Among them, the functions of the C51 core registers are
outlined below. More information on the use of the other standard SFRs is included in the description of those
peripherals.
6.2.1. C51 Core Registers
Accumulator: ACC is the Accumulator register. The mnemonics for Accumulator-Specific instructions, however,
refer to the Accumulator simply as A.
B Register: The B register is used during multiply and divide operations. For other instructions it can be treated
as another scratch pad or general purpose register.
Stack Pointer: The Stack Pointer register is 8 bits wide. It denotes the top of the Stack, which is the last used
value. The user can place the Stack anywhere in the internal scratchpad RAM by setting the Stack Pointer to
the desired location, although the lower bytes are normally used for working registers. On reset, the Stack
Pointer is initialized to 07H. This causes the stack to begin at location 08H.
Data Pointer: The Data Pointer (DPTR) consists of a high byte (DPH) and a low byte (DPL). Its intended
function is to hold a 16-bit address to assign a memory address for the MOVX instructions. This address can
point to a program/data memory location, either on- or off-chip, or a memory-mapped peripheral. It may be
manipulated as a 16-bit register or as two independent 8-bit registers.
PSW (Address=D0H, Program Status Word, Reset Value=0000_0000B)
7
6
5
4
3
2
1
0
CY
AC
F0
RS1
RS2
OV
-
P
CY: Carry flag.
This bit is set when the last arithmetic operation resulted in a carry (addition) or a borrow (subtraction).It is
cleared to logic 0 by all other arithmetic operations.
AC: Auxiliary Carry flag. (For BCD Operations)
This bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction)
the high order nibble. It is cleared to logic 0 by all other arithmetic operations.
F0: Flag 0.
This is a bit-addressable, general purpose flag for use under firmware control.
RS0~1: Register bank select bit 0~1.
Table 6-2 Register bank select table
{RS1, RS0} Working Resister Bank and Address
(0, 0)
(0, 1)
(1, 0)
(1, 1)
Bank 0 (00H~07H)
Bank 1 (08H~0FH)
Bank 2 (10H~17H)
Bank 3 (18H~1FH)
OV: Overflow flag.
This bit is set to 1 under the following circumstances:
• An ADD, ADDC, or SUBB instruction causes a sign-change overflow.
• An MUL instruction results in an overflow (result is greater than 255).
• A DIV instruction causes a divide-by-zero condition.
The OV bit is cleared to 0 by the ADD, ADDC, SUBB, MUL, and DIV instructions in all other cases.
P: Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even number of “one” bits in the Accumulator,
i.e., even parity.
18
MG84FL54B Data Sheet
MEGAWIN