MG84FL54BD Datasheet, PDF (88/113 Pages) Megawin Technology Co., Ltd – Four and half configurable I/O ports

19. Universal Serial Bus (USB)
MG84FL54B implements a USB full-speed function which is fully compliable with USB specification 2.0 and 1.1
to support various usb applications. The USB block contains a USB transceiver which transmits and receives
differential usb signal, a 256 bytes FIFO which is a temporary store data unit, and a USB Core to perform NRZI
encoding and decoding, bit stuffing, CRC generation and checking, serial-parallel data transforming, data flow
between 256 bytes FIFO and uC, usb special function register and setting, and communication with CPU by
MOVX instruction.
Before using MG84FL54B USB function, we assume that user has a comprehensive understanding on USB
protocol and application. So, the following descriptions in this chapter would not focus on the detail of USB
specification. If user is interesting in USB specification, user can download the latest version of USB
specification document from the usb official website http://www.usb.org/home.
Megawin Inc. also offer a development kit which contain sample code, C language library and application note
on the website http://www.megawin.com.tw/ to help user to implement design more quickly and easily.
Note:
MG84FL54B can’t be used as a USB HOST device or USB OTG device.
19.1. USB Block Diagram
Fig 19-1 USB Block Diagram
DP
USB
DM
Transceiver
USB Core
MOVX
1T 8051 Core
256 bytes FIFO
19.2. USB FIFO Management
A total of 4 endpoints are available in MG84FL54B as shown in Fig 19-2. Endpoint 0 supports a bi-direction
control transfer. Endpoint 1 supports Interrupt/Bulk IN transaction. Endpoint 2 supports Interrupt/Bulk or
Isochronous IN transaction. Endpoint 3 supports Interrupt/Bulk IN or OUT transaction depends on the setting of
EP3DIR in DCON register. Endpoint 3 also has additional function to support Isochronous OUT transaction.
There are 256 bytes FIFO for temporary usb data store unit accessed by USB core and Fig 19-2 shows the
USB FIFO configuration. Endpoint 2 and 3 support Dual Buffer mode by the setting of TXDBM and RXDBM in
EPCON register. In Non Dual Buffer mode, each endpoint has 64 bytes FIFO space and the maximum data
packet size can be up to 64 bytes. In Dual Buffer mode, the 64 bytes FIFO for endpoint 2 and 3 would be split to
two 32 bytes bank to improve the usage of FIFO.
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MG84FL54B Data Sheet
MEGAWIN