MG84FL54BD Datasheet, PDF (95/113 Pages) Megawin Technology Co., Ltd – Four and half configurable I/O ports

Fig 19-4 EPINDEX switch function
Endpoint 0
Endpoint 1
Endpoint 2
Endpoint 3
EPCON
RXSTAT
TXSTAT
RXDAT
TXDAT
RXCON
TXCON
RXCNT
TXCNT
CPU R/W
EPINDEX
EPCON (Endpoint Control Register, Endpoint-Indexed, Address=E1H, SYS/USB_reset=0000-0000, Read/Write)
7
6
5
4
3
2
1
0
RXSTL TXSTL RXDBM TXDBM RXISO RXEPEN TXISO TXEPEN
Bit7: RXSTL-- Receive Endpoint Stall.
Set this bit to stall the receive endpoint. When this bit is set, Device will response STALL packet to
upstream host in the handshake phase except when control setup transaction happen or RXSETUP=1.
Bit6: TXSTL-- Transmit Endpoint Stall.
Set this bit to stall the transmit endpoint.
Bit5: RXDBM-- Receive Endpoint Dual Buffer Mode.
Set this bit to enable the dual buffer transfer for OUT transaction. Default is cleared.
This bit is only valid for endpoint 3 receive mode.
Bit4: TXDBM-- Transmit Endpoint Dual Buffer Mode.
Set this bit to enable the dual buffer transfer for IN transaction. Default is cleared.
This bit is only valid for endpoint 2.
Bit3: RXISO-- Receive Isochronous Type Enable.
Set this bit to configure the endpoint for Isochronous-Out transfer type. When disabled, the endpoint is for
Bulk/Interrupt-Out transfer type. The default value is 0.
This bit is only valid for endpoint 3 receive mode.
Bit2: RXEPEN-- Receive Endpoint Enable.
Set this bit to enable the receive endpoint. When disabled, the endpoint does not respond to a valid OUT
or SETUP token. This bit in endpoint 0 is enabled after reset.
Bit1: TXISO-- Transmit Isochronous Type Enable.
Set this bit to configure the endpoint for Isochronous-In transfer type. When disabled, the endpoint is for
Bulk/Interrupt-In transfer type. The default value is 0.
This bit is only valid for endpoint 2.
Bit0: TXEPEN-- Transmit Endpoint Enable.
Set this bit to enable the transmit endpoint. When disabled, the endpoint does not respond to a valid IN
token. This bit in endpoint 0 is enabled after reset.
The following table lists the maximum data packet size for each endpoint FIFO configuration:
MEGAWIN
MG84FL54B Data sheet
95