MDT10P74 Datasheet, PDF (18/24 Pages) Micon Design Technology Corporation – 8-bit micro-controller

Register
Address
Power-On Reset,
Power range detector
Reset
/MCLR or WDT Reset
SCMSTA
94h
---- ---0
---- ---0
TXSC
98h
0000 -010
0000 -010
BRREG
99h
0000 0000
0000 0000
ADS1
9Fh
---- -000
---- -000
Note : u unchanged, x unknown, - unimplemented, read as “0”
# value depends on the condition of the following table
MDT10P74
Wake-up from SLEEP
---- ---u
uuuu -uuu
uuuu uuuu
---- -uuu
Condition
Status: bit 4
Status: bit 3
/MCLR reset (not during SLEEP)
u
u
/MCLR reset during SLEEP
1
0
WDT reset (not during SLEEP)
0
1
WDT reset during SLEEP
0
0
Power-on reset
1
1
Power-range reset
1
1
Note : u unchanged, x unknown, - unimplemented, read as “0”
8. Instruction Set :
PSTA: bit 1
u
u
u
u
0
u
PSTA: bit 0
u
u
u
u
x
0
Instruction Code
010000 00000000
010000 00000001
010000 00000010
010000 00000011
010000 00000100
010000 00000rrr
010001 1rrrrrrr
011000 trrrrrrr
111010 iiiiiiii
010111 trrrrrrr
011001 trrrrrrr
011010 trrrrrrr
011011 trrrrrrr
Mnemonic
Operands
NOP
CLRWT
SLEEP
TMODE
RET
CPIO R
STWR R
LDR R, t
LDWI I
SWAPR R, t
INCR R, t
INCRSZ R, t
ADDWR R, t
Function
Operating
No operation
None
Clear Watchdog timer
0 WT
Sleep mode
0 WT, stop OSC
Load W to TMODE register W TMODE
Return from subroutine
Stack PC
Control I/O port register
W CPIO r
Store W to register
WR
Load register
Rt
Load immediate to W
IW
Swap halves register
[R(0~3) ↔R(4~7)] t
Increment register
R+1 t
Increment register, skip if zero R + 1 t
Add W and register
W+R t
Status
TF, PF
TF, PF
None
None
None
None
Z
None
None
Z
None
C, HC, Z
This specification are subject to be changed without notice. Any latest information
please preview http;//www.mdtic.com.tw
P. 18
(Preliminary)
2005/6 Ver. 1.5