8143 Datasheet, PDF (9/24 Pages) Maxwell Technologies – 12-Bit Serial Daisy Chain D/A Converter

12-Bit Serial Daisy-Chain D/A Converter
FIGURE 9. DIGITAL OUTPUT VOLTAGE VS. OUTPUT CURRENT
8143
Definition of Specifications
The resolution of a DAC is the number of states (2ⁿ) into which the full-scale range (FSR) is divided (or resolved),
where “n” is equal to the number of bits.
Settling Time
Time required for the analog output of the DAC to settle to within 1/2 LSB of its final value for a given digital input stim-
ulus; i.e., zero to full-scale.
Gain
Ratio of the DAC’s external operational amplifier output voltage to the V_REF input voltage when all digital inputs are
HIGH.
Feedthrough Error
Error caused by capacitive coupling from V_REF to output. Feedthrough error limits are specified with all switches off.
Output Capacitance
Capacitance from I_OUT1 to ground.
Output Leakage Current
Current appearing at I_OUT1 when all digital inputs are LOW, or at IOUT₂ terminal when all inputs are HIGH.
General Circuit Information
The 8143 is a 12-bit serial-input, buffered serial-output, multiplying CMOS D/A converter. It has an R-2R resistor lad-
der network, a 12-bit input sift register, 12-bit DAC register, control logic circuitry, and a buffered digital output stage.
The control logic forms an interface in which serial data is loaded, under microprocessor control, into the input sift reg-
ister and then transferred, in parallel, to the DAC register. In addition, buffered serial output data is present at the SRO
pin when input data is loaded into the input register. This buffered data follows the digital input data (SRI) by 12 clock
cycles and is available for daisy-chaining additional DACs.
07.23.03 REV 3
All data sheets are subject to change without notice 9
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