8143 Datasheet, PDF (19/24 Pages) Maxwell Technologies – 12-Bit Serial Daisy Chain D/A Converter

12-Bit Serial Daisy-Chain D/A Converter
FIGURE 20. ANALOG/DIGITAL DIVIDER
8143
Application Tips
In most applications, linearity depends on the potential of I_OUT1, I_OUT2, and AGND (Pins 1, 2 and 3) being exactly equal
to each other. In most applications, the DAC is connected to an external Op Amp with its noninverting input tied to
ground (see Figures 16 and 17). The amplifier selected should have a low input bias current and low drift over temper-
ature. The amplifier’s input offset voltage should be nulled to less than ±200 µ V (less than 10% of 1 LSB).
The operational amplifier’s noninverting input should have a minimum resistance connection to ground; the usual bias
current compensation resistor should not be used. This resistor can cause a variable offset voltage appearing as a
varying output error. All grounded pins should tie to a single common ground point, avoiding ground loops. The V_DD
power supply should have a low noise level with no transients greater than 17V.
It is recommended that the digital input be taken to ground or V_DD via a high value (1 MΩ) resistor, this will prevent the
accumulation of static charge if the PC card is disconnected from the system.
Peak supply current flows as the digital input pass through the transition region (see Figure 4). The supply current
decreases as the input voltage approaches the supply rails (V_DD or DGND), i.e., rapidly slewing logic signals that settle
very near the supply rails will minimize supply current.
Interfacing to the MC6800
As shown in Figure, the 8143 may be interfaced to the 6800 by successively executing memory WRITE instruction
while manipulating the data between WRITEs, so that each WRITE presents the next bit.
In this example, the most significant bits are found in memory locations 0000 and 0001. The four MSBs are found in
the lower half of 0000, the eight LSBs in 0001. The data is taken from the DB₇ line.
The serial data loading is triggered by STB₄ which is asserted by a decoded memory WRITE to a memory location, R/
W, and f2. A WRITE to another address location transfers data from input register to DAC register.
07.23.03 REV 3
All data sheets are subject to change without notice 19
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