DS80C400_03 Datasheet, PDF (93/96 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
Status
The STATUS (C5h) register and STATUS1 (F7h) register provide information about interrupt and serial port activity
to assist in determining if it is possible to enter PMM. The microcontroller supports three levels of interrupt priority:
power-fail, high, and low. The PIP (power-fail priority interrupt status; STATUS.7), HIP (high priority interrupt status;
STATUS.6), and LIP (low priority interrupt status; STATUS.5) status bits, when set to a logic 1, indicate the
corresponding level is in service.
Software should not rely on a lower-priority level interrupt source to remove PMM (switchback) when a higher level
is in service. Check the current priority service level before entering PMM. If the current service level locks out a
desired switchback source, then it would be advisable to wait until this condition clears before entering PMM.
Alternately, software can prevent an undesired exit from PMM by intentionally entering a low priority interrupt-
service level before entering PMM. This prevents other low priority interrupts from causing a switchback.
Entering PMM during an ongoing serial port transmission or reception can corrupt the serial port activity. To
prevent this, a hardware lockout feature ignores changes to the clock divisor bits while the serial ports are active.
Serial port transmit and receive activity can be monitored through the serial port activity bits located in the STATUS
and STATUS1 registers.
Oscillator-Fail Detect
The microcontroller contains a safety mechanism called an on-chip oscillator-fail detect circuit. When enabled, this
circuit causes the microcontroller to be held in reset if the oscillator frequency falls below ~100kHz. When
activated, this circuit complements the watchdog timer. Normally, the watchdog timer is initialized so that it times
out and causes a reset in the event that the microcontroller loses control. In the event of a crystal or external
oscillator failure, however, the watchdog timer does not function, and there is the potential to fail in an uncontrolled
state. Using the oscillator-fail detect circuit forces the microcontroller to a known state (i.e., reset) even if the
oscillator stops.
The oscillator-fail detect circuitry is enabled when software sets the enable bit OFDE (PCON.4) to a 1. Please note
that software must use a timed-access procedure (described earlier) to write this bit. The OFDF (PCON.5) bit also
sets to a 1 when the circuitry detects an oscillator failure, and the microcontroller is forced into a reset state. This
bit can only be cleared to a 0 by a power-fail reset or by software. The oscillator-fail detect circuitry is not triggered
when the oscillator is stopped upon entering stop mode.
Power-Fail Reset
The microcontroller incorporates an internal precision bandgap voltage reference and comparator circuit that
provide a power-on and power-fail reset function. This circuit monitors the incoming power supply voltages (V_CC1
and V_CC3) and holds the microcontroller in reset if either supply is below a minimum voltage level. When power
exceeds the reset threshold, a full power-on reset is performed. In this way, this internal voltage monitoring circuitry
handles both power-up and power-down conditions without the need for additional external components.
Once V_CC1 and V_CC3 have risen above minimum voltages, V_RST1 and V_RST3 respectively, the device automatically
restarts the oscillator for the external crystal and counts 65,536 clock cycles before program execution begins at
location 0000h. This helps the system maintain reliable operation by only permitting operation when the supply
voltage is in a known good state. Software can determine that a power-on reset has occurred by checking the
power-on reset flag (POR;WDCON.6). Software should clear the POR bit after reading it.
Power-Fail Interrupt
The bandgap voltage reference that sets precise reset thresholds also generates an optional early warning power-
fail interrupt (PFI). When enabled by software, the microcontroller vectors to code address 0033h if either V_CC1 or
V_CC3 drop below V_PFW1 or V_PFW3, respectively. PFI has the highest priority. The PFI enable is in the watchdog
control SFR (EPFI;WDCON.5). Setting this bit to logic 1 enables the PFI. Application software can also read the
PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt enable and must
be cleared by software.
93 of 96