DS80C400_03 Datasheet, PDF (13/96 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
ELECTRICAL CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS)
(Note 1)
(V_CC3 = 3.0V to 3.6V, V_CC1 = 1.8V ±10%, T_A = -40∞C to +85∞C.)
PARAMETER
SYMBOL
75MHz
MIN MAX
External Crystal Frequency
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
External Oscillator Frequency
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
PSEN Pulse Width
PSEN Low to Valid Instruction In
Input Instruction Hold After PSEN
1 / tCLK
1 / tCLK
tPLPH
tPLIV
tPXIX
21.7
9.7
0
Input Instruction Float After PSEN
tPXIZ
Port 7 Address to Valid Instruction In
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
tAVIV1
tAVIV2
21.0
27.7
VARIABLE CLOCK
MIN
MAX
4
40
16
37.5
11
18.75
DC
75
16
37.5
11
18.75
2tCLCL - 5
2tCLCL - 17
0
See MOVX
Characteristics
3tCLCL - 19
3tCLCL + tCLCH - 19
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
Note 1: Specifications to -40∞C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3: tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in the
the System Clock Time Periods table.
Note 4: The precalculated 75MHz min/max timing specifications assume an exact 50% duty cycle.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16ñA19), Port 5.4ñ5.7
(PCE0-3), Port 6.0ñ6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0ñA7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
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