DS80C400_03 Datasheet, PDF (14/96 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
MOVX CHARACTERISTICS (NONMULTIPLEXED ADDRESS/DATA BUS) (Note 1)
(V_CC3 = 3.0V to 3.6V, V_CC1 = 1.8V +±10%, T_A = -40∞C to +85∞C.)
PARAMETER
SYMBOL
MIN
Input Instruction Float After PSEN
tPXIZ
PSEN High to Data Address, Port 4 CE,
Port 5 PCE Valid
RD Pulse Width (P3.7 or PSEN)
tPHAV
tRLRH
WR Pulse Width (P3.6)
tWLWH
RD (P3.7 or PSEN) Low to Valid Data In
Data Hold After RD (P3.7 or PSEN) High
tRLDV
tRHDX
Data Float After RD (P3.7 or PSEN) High tRHDZ
PSEN High to WR Low
tPHWL
PSEN High to (RD or PSEN) Low
tPHRL
Port 7 Address to Valid Data In
tAVDV1
tCHCL - 3
2tCLCL - 5
(4 x CST) tCLCL - 3
2tCLCL - 5
(4 x CST)tCLCL - 3
-2
2tCLCL - 3
3tCLCL - 3
11tCLCL - 3
2tCLCL - 3
3tCLCL - 3
11tCLCL - 3
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to Valid Data In
tAVDV2
Port 7 Address to (RD or PSEN) or WR
Low
tAVWL1
Port 2, 4, 6 Address, Port 4 CE or Port 5
PCE to (RD or PSEN) or WR Low
Data Valid to WR Transition
Data Hold After WR High
tAVWL2
tQVWX
tWHQX
(RD or PSEN) or WR High to Port 4 CE
or Port 5 PCE High
tWHCEH
tCLCL - 5
2tCLCL - 5
10tCLCL - 5
tCLCL + tCLCH - 5
2tCLCL + tCLCH - 5
10tCLCL + tCLCH - 5
0
tCLCL - 4
2CLCL - 7
6tCLCL - 7
tCHCL - 5
tCLCL + tCHCL - 5
5tCLCL + tCHCL -5
MAX
UNITS
2tCLCL - 5
3tCLCL - 5
ns
11tCLCL - 5
ns
ns
ns
2tCLCL - 17
ns
(4 x CST)tCLCL - 17
ns
tCLCL - 5
2tCLCL - 5
ns
6tCLCL - 5
ns
ns
3tCLCL - 19
(4 x CST + 2)tCLCL- 19
ns
(4 x CST + 10)tCLCL -
19
3tCLCL + tCLCH - 19
(4 x CST + 2)tCLCL +
tCLCH - 19
ns
(4 x CST + 10)tCLCL +
tCLCH - 19
ns
ns
ns
ns
tCHCL + 13
tCLCL + tCHCL +12
ns
5tCLCL + tCHCL +12
STRETCH
VALUES
CST (MD2:0)
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST =0
1 £ CST £ 7
CST =0
1 £ CST £ 7
CST = 0
1 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1£ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
CST = 0
1 £ CST £ 3
4 £ CST £ 7
Note 1: Specifications to -40∞C are guaranteed by design and not production tested.
Note 2: All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Note 3: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL, tCLCH, tCHCL are time periods
associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 4: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16ñA19), Port 5.4ñ5.7
(PCE0-3), Port 6.0ñ6.5 (CE4-7, A20, A2), Port 7 (demultiplexed mode A0ñA7).
Note 5: References to the XTAL or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not for determing
absolute signal timing with respect to the external clock.
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