DS80C400_03 Datasheet, PDF (79/96 Pages) Maxim Integrated Products – Network Microcontroller

DS80C400 Network Microcontroller
Task Scheduler
The TINI400 ROM firmware implements a priority based preemptive task scheduler. Each task created is
represented in a task ring by a corresponding task control block (TCB). The TCB holds critical information specific
to the task, such as the ID, priority, event bit mask, wake-up time, and pointers to state information and next task.
Using a timer, the scheduler is run approximately every 4ms (at 18.432MHz crystal frequency) unless deferred
because another interrupt is in progress. The scheduler supports an unlimited number of tasks and allows addition,
deletion, or modification on the fly. However, one should realize that increasing the number of tasks increases the
time needed by the scheduler to search and prioritize the ring. The High-Speed Microcontroller Userís Guide:
DS80C400 Supplement provides greater detail about the task scheduler and its functionality.
Controller Area Network (CAN) Module
The DS80C400 incorporates one CAN controller that is fully compliant with the CAN 2.0B specification. CAN is a
highly robust, high-performance communication protocol for serial communications. Popular in a wide range of
applications including automotive, medical, heating, ventilation, and industrial control, the CAN architecture allows
for the construction of sophisticated networks with a minimum of external hardware.
The CAN controller supports the use of 11-bit standard or 29-bit extended acceptance identifiers for up to 15
messages, with the standard 8-Byte data field, in each message. Fourteen of the 15 message centers are
programmable in either transmit or receive modes, with the 15th designated as an FIFO-buffered, receive-only
message center to help prevent data overruns. All message centers have two separate 8-bit media masks and
media arbitration fields for incoming message verification. This feature supports the use of higher-level protocols
that use the first and/or second byte of data as a part of the acceptance layer for storing incoming messages. Each
message center can also be programmed independently to test incoming data with or without the use of the global
masks.
Global controls and status registers in the CAN unit allow the microcontroller to evaluate error messages, generate
interrupts, locate and validate new data, establish the CAN bus timing, establish identification mask bits, and verify
the source of individual messages. Each message center is individually equipped with the necessary status and
control bits to establish direction, identification mode (standard or extended), data field size, data status, automatic
remote frame request and acknowledgment, and perform masked or nonmasked identification-acceptance testing.
Communicating with the CAN Module
The microcontroller interface to the CAN modules is divided into two groups of registers. All the global CAN status
and control bits as well as the individual message center control/status registers are located in the SFR map. The
remaining registers associated with the message centers (data identification, identification/arbitration masks, format
and data) are located in MOVX data space. The CMA bit (MCON.5) allows the message centers to be mapped to
either 00DB00hñ00DBFFh (CMA = 0) or FFDB00hñFFDBFFh (CMA = 1), reducing the possibility of a memory
conflict with application software. The internal architecture of the DS80C400 requires that the device be in one of
the two 24-bit addressing modes when the CMA bit is set to correctly access the CAN MOVX memory. A special
lockout feature prevents the accidental software corruption of the control, status, and mask registers while a CAN
operation is in progress. Each CAN controller uses a total of 15 message centers. Each message center is
composed of four specific areas that include the following:
1) Four arbitration registers (C0MxAR0-3) that store either the 11-bit or 29-bit arbitration value. These registers
are located in the MOVX memory map.
2) A format register (C0MxF) that informs the CAN controller as to the direction (transmit or receive), the number
of data bytes in the message, the identification format (standard or extended), and the optional use of the
identification mask or media mask during message evaluation. This register is located in the MOVX memory
map.
3) Eight data bytes for storage of 0 to 8 Bytes of data (C0MxD0ñ7) are located in the MOVX memory map.
4) Message control registers (C0MxC) are located in the SFR memory for fast access.
Each of the message centers is identical with the exception of message center 15. Message center 15 has been
designed as a receive-only center and is also buffered through the use of a two-message FIFO to help prevent
message loss in a message-overrun situation. The receipt of a third message before either of the first two are read
overwrites the second message, leaving the first message undisturbed.
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