MAX14720 Datasheet, PDF (9/38 Pages) Maxim Integrated Products – Extended System Battery Use Time

MAX14720/MAX14750
Power-Management Solution
Electrical Characteristics (continued)
(V_CC = V_BIN = V_LIN = V_HVIN = V_SWIN = 2.7V, T_A = -40°C to +85°C, all registers in their default state, unless otherwise noted. Typical
values are at T_A = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Digital Signals (V_CC = 1.8V to 5.5V, unless otherwise noted. Typical values are at V_CC = 2.7V.)
Input Logic-High (SDA,
SCL,SWEN,KIN,
V_IH
No seal mode
1.4
BEN,MPC,LEN,HVEN)
MAX
UNITS
V
Input Logic-Low (SDA,
SCL,SWEN,KIN,
BEN,MP,LEN,HVEN)
No seal mode
V_IL
No seal mode, V_CC ≥ 2.7V
0.45
V
0.5
V
Input Logic-High, Seal
Seal mode
4.1
V
Mode (SDA, SCL, KIN,
MPC)
V_{IH_SEAL}
Seal mode, V_CC ≥ 2.7V
2.2
V
Input Logic-Low,
Seal Mode (SDA, SCL,
KIN, MPC)
V_{IL_SEAL}
Seal mode
0.5
V
Output Logic-Low
(SDA, RST, KOUT)
V_OL
I_OL = 4mA
0.4
V
SCL Clock Frequency
KIN Pullup Resistance
Bus Free Time Between
a Stop and Start
Condition
f_SCL
R_KIN
t_BUF
0
400
kHz
210
kΩ
1.3
µs
Start Condition
(Repeated) Hold Time
t_HD:STA
(Note 3)
0.6
µs
Low Period of SCL
Clock
t_LOW
1.3
µs
High Period of SCL
Clock
t_HIGH
0.6
µs
Setup Time for a
Repeated Start
Condition
t_SU:STA
0.6
µs
Data Hold Time
Data Setup Time
Setup Time for Stop
Condition
t_HD:DAT
t_SU:DAT
t_SU:STO
(Note 4)
0
0.9
µs
100
ns
0.6
µs
Spike Pulse Widths
Suppressed by Input
t_SP
Filter
50
ns
Note 2: All devices are 100% production tested at T_A = +25°C. Limits over the operating temperature range are guaranteed by
design.
Note 3: f_SCL must meet the minimum clock low time plus the rise/fall times.
Note 4: The maximum t_HD:DAT has to be met only if the device does not stretch the low period (t_LOW) of the SCL signal.
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