MAX14720 Datasheet, PDF (28/38 Pages) Maxim Integrated Products – Extended System Battery Use Time

MAX14720/MAX14750
Power-Management Solution
I²C Interface
The MAX14720/MAX14750 contain an I²C-compatible
interface for data communication with a host controller
(SCL and SDA). The interface supports a clock frequency
of up to 400kHz. SCL and SDA require pullup resistors
that are connected to a positive supply.
Start, Stop, And Repeated Start Conditions
When writing to the MAX14720/MAX14750 using I²C,
the master sends a START condition (S) followed by the
MAX14720/MAX14750 I²C address. After the address,
the master sends the register address of the register that
is to be programmed. The master then ends communication
by issuing a STOP condition (P) to relinquish control
of the bus, or a REPEATED START condition (Sr) to
communicate to another I²C slave. See Figure 4.
Table 26. I²C Slave Addresses
ADDRESS FORMAT
7-Bit Slave ID
Write Address
Read Address
HEX
0x2A
0x54
0x55
BINARY
0101010
0000 0100
01010101
S
SCL
Sr
P
SDA
Slave Address
Set the Read/Write bit high to configure the devices
to read mode (Table 26). Set the Read/Write bit low to
configure the MAX14720/MAX14750 to write mode.
The address is the first byte of information sent to the
MAX14720/MAX14750 after the START condition.
Bit Transfer
One data bit is transferred on the rising edge of each
SCL clock cycle. The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes in
SDA while SCL is high and stable are considered control
signals (see the Start, Stop, And Repeated Start Conditions
section). Both SDA and SCL remain high when the bus
is not active.
Single-Byte Write
In this operation, the master sends an address and two
data bytes to the slave device (Figure 5). The following
procedure describes the single byte write operation:
1) The master sends a START condition
2) The master sends the 7-bit slave address plus a
write bit (low)
3) The addressed slave asserts an ACK on the data
line
4) The master sends the 8-bit register address
5) The slave asserts an ACK on the data line only if the
address is valid (NAK if not)
6) The master sends 8 data bits
7) The slave asserts an ACK on the data line
8) The master generates a STOP condition
Figure 4. I²C START, STOP, and REPEATED START Conditions
WRITE SINGLE BYTE
S
DEVICE SLAVE ADDRESS - W A
REGISTER ADDRESS
A
8 DATA BITS
A
P
FROM MASTER TO SLAVE
Figure 5. Write Byte Sequence
FROM SLAVE TO MASTER
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