MAX1270BCAI Datasheet, PDF (9/20 Pages) Maxim Integrated Products – Multirange, +5V, 8-Channel, Serial 12-Bit ADCs

Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
+5V
+5V
100kΩ
24kΩ
510kΩ
0.01µF
MAX1270
MAX1271
REFADJ
DOUT
OR
SSTRB
0.5mA
C_LOAD
5mA
DOUT
OR
SSTRB
C_LOAD
a) HIGH IMPEDANCE TO V_OH, V_OL TO b) HIGH IMPEDANCE TO V_OH, V_OL TO
V_OH AND V_OH TO HIGH IMPEDANCE
V_OH AND V_OH TO HIGH IMPEDANCE
Figure 1. Reference-Adjust Circuit
Detailed Description
Converter Operation
The MAX1270/MAX1271 multirange, fault-tolerant ADCs
use successive approximation and internal track/hold
(T/H) circuitry to convert an analog signal to a 12-bit
digital output. Figure 3 shows the block diagram of the
MAX1270/MAX1271.
Analog-Input Track/Hold
The T/H enters tracking/acquisition mode on the falling
edge of the sixth clock in the 8-bit input control word,
and enters hold/conversion mode when the timed
acquisition interval (six clock cycles, 3µs minimum)
ends. In internal clock mode, the acquisition is timed by
two external clock cycles and four internal clock cycles.
Figure 2. Output Load Circuit for Timing Characteristics
When operating in bipolar (MAX1270 and MAX1271) or
unipolar mode (MAX1270) the signal applied at the
input channel is rescaled through the resistor-divider
network formed by R1, R2, and R3 (Figure 4); a low
impedance (<4Ω) input source is recommended to
minimize gain error. When the MAX1271 is configured
for unipolar mode, the channel input resistance (R_IN)
becomes a fixed 5.12kΩ (typ). Source impedances
below 15kΩ (0 to V_REF) and 5kΩ (0 to V_REF/2) do not
significantly affect the AC performance of the ADC.
The acquisition time (t_ACQ) is a function of the source
output resistance, the channel input resistance, and the
T/H capacitance. Higher source impedances can be
used if an input capacitor is connected between the
analog inputs and AGND. Note that the input capacitor
forms an RC filter with the input source impedance, lim-
iting the ADC’s signal bandwidth.
DIN SSTRB DOUT CS
SCLK
SHDN
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
REF
REFADJ
ANALOG
INPUT
MUX
AND SIGNAL
CONDITIONING
2.5V
REFERENCE
10kΩ
SERIAL INTERFACE LOGIC
INT
CLOCK
T/H
Av =
1.638
+4.096V
OUT
IN
REF
CLOCK
12-BIT SAR ADC
MAX1270
MAX1271
V_DD
AGND
DGND
Figure 3. Block Diagram
_______________________________________________________________________________________ 9