MAX1270BCAI Datasheet, PDF (13/20 Pages) Maxim Integrated Products – Multirange, +5V, 8-Channel, Serial 12-Bit ADCs

Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
t_SDV
SSTRB HIGH-Z
SCLK
SCLK 12
Figure 7. External Clock Mode—SSTRB Detailed Timing
t_SSTRB
t_SSTRB
t_STR
HIGH-Z
CS
SCLK 1
8
MSB
CONTROL BYTE 0
LSB
DIN ^{START SEL2 SEL1 SEL0 RNG BIP PD1 PD0}
HIGH-Z
SSTRB
18 SCLK
HIGH-Z
DOUT
A/D STATE
ACQUISITION
6 SCLK
13 14
16
19
24
26
CONTROL BYTE 1
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
MSB
RESULT
LSB
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONVERSION
12 SCLK
18 SCLK
ACQUISITION
6 SCLK
31 32
37
CONTROL BYTE 2
START SEL2
RESULT 1
D11 D10 D9 D8 D7 D6 D5
CONVERSION
12 SCLK
Figure 8. External Clock Mode—18 Clocks/Conversion Timing
Internal Clock Mode (PD1 = 0, PD0 = 0)
In internal clock mode, the MAX1270/MAX1271 gener-
ate their conversion clock internally. This frees the
microprocessor from the burden of running the acquisi-
tion and the SAR conversion clock, and allows the con-
version results to be read back at the processor’s
convenience, at any clock rate from 0 to typically
10MHz.
SSTRB goes low after the falling edge of the last bit
(PD0) of the control byte has been shifted in, and
returns high when the conversion is complete.
Acquisition is completed and conversion begins on the
falling edge of the 4th internal clock pulse after the con-
trol byte; conversion ends on the falling edge of the
16th internal clock pulse (12 internal clock cycle pulses
are used for conversion). SSTRB will remain low for a
maximum of 15µs, during which time SCLK should
remain low for best noise performance. An internal reg-
ister stores data while the conversion is in progress.
The MSB of the result byte (D11) is present at DOUT
starting at the falling edge of the last internal clock of
conversion. Successive falling edges of SCLK will shift
the remaining data out of this register (Figure 9).
Additional SCLK edges will result in zeros on DOUT.
When internal clock mode is selected, SSTRB does not
go into a high-impedance state when CS goes high.
Pulling CS high prevents data from being clocked in
and tri-states DOUT, but does not adversely affect a
______________________________________________________________________________________ 13