MAX1270BCAI Datasheet, PDF (8/20 Pages) Maxim Integrated Products – Multirange, +5V, 8-Channel, Serial 12-Bit ADCs

Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
Typical Operating Characteristics (continued)
(Typical Operating Circuit, V_DD = +5V; external reference mode, V_REF = +4.096V; 4.7µF at REF; external clock, f_CLK = 2MHz;
110ksps; T_A = +25°C, unless otherwise noted.)
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING STANDBY)
8
V_DD = 5V, INTERNAL REFERENCE,
7 fCLK = 2MHz
EXTERNAL CLOCK MODE.
6 LOW-RANGE UNIPOLAR MODE.
V_{CH_} = 0
5
AVERAGE SUPPLY CURRENT vs.
CONVERSION RATE (USING FULLPD)
8
V_DD = 5V, INTERNAL REFERENCE,
7 fCLK = 2MHz
EXTERNAL CLOCK MODE.
6 LOW-RANGE UNIPOLAR MODE.
V_{CH_} = 0
5
4
4
3
3
2
2
1
1
0
0.1
1
10
100
1000
CONVERSION RATE (ksps)
0
0.1
1
10
100
1000
CONVERSION RATE (ksps)
Pin Description
PIN
PDIP SSOP
1
1
2, 4
2, 3
3, 9,
22, 24
4, 7, 8,
11, 22,
24, 25, 28
5
5
6
6
7
9
NAME
V_DD
DGND
N.C.
SCLK
CS
DIN
FUNCTION
+5V Supply. Bypass with a 0.1µF capacitor to AGND.
Digital Ground
No Connection. No internal connection.
Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also
sets the conversion speed.
Active-Low Chip-Select Input. Data is not clocked into DIN unless CS is low. When CS is high,
DOUT is high impedance.
Serial Data Input. Data is clocked in on the rising edge of SCLK.
Serial Strobe Output. In internal clock mode, SSTRB goes low after the falling edge of the eighth
8
10
SSTRB
SCLK and returns high when the conversion is done. In external clock mode, SSTRB pulses high
for one clock period before the MSB decision. High impedance when CS is high in external
clock mode.
10
12
DOUT ^{Serial Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is}
high.
11
13
SHDN Shutdown Input. When low, device is in FULLPD mode. Connect high for normal operation.
12
14
AGND Analog Ground
13–20 15–21, 23 CH0–CH7 Analog Input Channels
21
26
REFADJ
Bandgap Voltage-Reference Output/External Adjust Pin. Bypass with a 0.01µF capacitor to AGND.
Connect to V_DD when using an external reference at REF.
23
27
Reference-Buffer Output/ADC Reference Input. In internal reference mode, the reference buffer
REF provides a 4.096V nominal output, externally adjustable to REFADJ. In external reference mode,
disable the internal reference by pulling REFADJ to V_DD and applying the external reference to REF.
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