MAX1270BCAI Datasheet, PDF (15/20 Pages) Maxim Integrated Products – Multirange, +5V, 8-Channel, Serial 12-Bit ADCs

Multirange, +5V, 8-Channel,
Serial 12-Bit ADCs
CS
SCLK
1
8
9
CONTROL BYTE Ø
DIN
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
14
16
CONTROL BYTE 1
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
22
24
CONTROL BYTE 2
START SEL2 SEL1 SEL0
13 SCLK
SSTRB
HIGH-Z
DOUT
A/D STATE
RESULT Ø
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RESULT 1
D11 D10 D9 D8 D7 D6 D5 D4 D3
ACQUISITION CONVERSION
13 SCLK
ACQUISITION CONVERSION
Figure 11. Internal Clock Mode—13 Clocks/Conversion Timing
CS
SCLK
1
8
9
CONTROL BYTE Ø
DIN
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
16 17
24
25
CONTROL BYTE 1
START SEL2 SEL1 SEL0 RNG BIP PD1 PD0
32
CB 2
START
16 SCLK
SSTRB
DOUT
HIGH-Z
RESULT Ø
HIGH-Z
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
RESULT 1
HIGH-Z _{D11 D10 D9 D8 D7 D6 D5 D4 D3}
A/D STATE
ACQUISITION CONVERSION
IDLE
16 SCLK
ACQUISITION CONVERSION
Figure 12. Internal Clock Mode—16 Clocks/Conversion Timing
Internal Reference
The internally trimmed 2.50V reference is amplified
through the REFADJ buffer to provide 4.096V at REF.
Bypass REF with a 4.7µF capacitor to AGND and
REFADJ with a 0.01µF capacitor to AGND (Figure 13a).
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
External Reference
To use the REF input directly, disable the internal buffer
by tying REFADJ to V_DD (Figure 13b). Using the
REFADJ input eliminates the need to buffer the refer-
ence externally. When a reference is applied at
REFADJ, bypass REFADJ with a 0.01µF capacitor to
AGND. Note that when an external reference is applied
at REFADJ, the voltage at REF is given by:
V_REF = 1.6384 x V_REFADJ (2.4 < V_REF < 4.18)
(Figure 13c). At REF and REFADJ, the input impedance
is a minimum of 10kΩ for DC currents. During conver-
sions, an external reference at REF must be able to deliv-
er 400µA DC load currents and must have an output
impedance of 10Ω or less. If the reference has higher
output impedance or is noisy, bypass REF with a 4.7µF
capacitor to AGND as close to the chip as possible.
With an external reference voltage of less than 4.096V
at REF or less than 2.5V at REFADJ, the increase in the
ratio of RMS noise to the LSB value (full-scale / 4096)
results in performance degradation (loss of effective
bits).
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